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Searched +full:esync +full:- +full:control (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/dpll/zl3073x/
H A Ddpll.c1 // SPDX-License-Identifier: GPL-2.0-only
28 * struct zl3073x_dpll_pin - DPLL pin
60 * Supported esync ranges for input and for output per output pair type
67 * zl3073x_dpll_is_input_pin - check if the pin is input one
75 return pin->dir == DPLL_PIN_DIRECTION_INPUT; in zl3073x_dpll_is_input_pin()
79 * zl3073x_dpll_is_p_pin - check if the pin is P-pin
82 * Return: true if the pin is P-pin, false if it is N-pin
87 return zl3073x_is_p_pin(pin->id); in zl3073x_dpll_is_p_pin()
98 *direction = pin->dir; in zl3073x_dpll_pin_direction_get()
108 struct dpll_pin_esync *esync, in zl3073x_dpll_input_pin_esync_get() argument
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H A Dprop.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * zl3073x_pin_check_freq - verify frequency for given pin
62 dev_warn(zldev->dev, in zl3073x_pin_check_freq()
69 * zl3073x_prop_pin_package_label_set - get package label for the pin
78 * REF<n> - differential input reference
79 * REF<n>P & REF<n>N - single-ende
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/linux/Documentation/devicetree/bindings/dpll/
H A Dmicrochip,zl30731.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ivan Vecera <ivecera@redhat.com>
15 single-ended inputs and 10 differential or 20 single-ended outputs.
21 - microchip,zl30731
22 - microchip,zl30732
23 - microchip,zl30733
24 - microchip,zl30734
25 - microchip,zl30735
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H A Ddpll-pin.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-pin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ivan Vecera <ivecera@redhat.com>
14 by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by
26 connection-type:
31 esync-control:
39 supported-frequencies-hz:
43 - reg
/linux/Documentation/netlink/specs/
H A Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
31 -
37 -
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c1 // SPDX-License-Identifier: GPL-2.0
53 * enum ice_dpll_pin_type - enumerate ice pin types:
71 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
83 * ice_dpll_is_sw_pin - check if given pin shall be controlled by SW
88 * Check if the pin shall be controlled by SW - instead of providing raw access
89 * for pin control. For E810 NIC with dpll there is additional MUX-related logic
95 * * true - pin controlled by SW
96 * * false - pin not controlled by SW
100 if (input && pf->hw.device_id == ICE_DEV_ID_E810C_QSFP) in ice_dpll_is_sw_pin()
101 index -= ICE_DPLL_SW_PIN_INPUT_BASE_QSFP - in ice_dpll_is_sw_pin()
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/linux/arch/xtensa/kernel/
H A Dentry.S2 * Low-level exception handling
8 * Copyright (C) 2004 - 2008 by Tensilica Inc.
17 #include <asm/asm-offsets.h>
22 #include <asm/asm-uaccess.h>
29 #include <variant/tie-asm.h>
34 * 100....0 -> 1
35 * 010....0 -> 2
36 * 000....1 -> WSBITS
42 nsau \bit, \mask # 32-WSBITS ... 31 (32 iff 0)
43 addi \bit, \bit, WSBITS - 32 + 1 # uppest bit set -> return 1
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