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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dfsl-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC)
7 by mmc.txt and the properties used by the sdhci-esdhc driver.
10 - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
12 "fsl,mpc8536-esdhc"
13 "fsl,mpc8378-esdhc"
14 "fsl,p2020-esdhc"
15 "fsl,p4080-esdhc"
16 "fsl,t1040-esdhc"
17 "fsl,t4240-esdhc"
19 "fsl,ls1012a-esdhc"
[all …]
H A Dfsl,esdhc.yaml4 $id: http://devicetree.org/schemas/mmc/fsl,esdhc.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC)
20 - fsl,mpc8536-esdhc
21 - fsl,mpc8378-esdhc
22 - fsl,p2020-esdhc
23 - fsl,p4080-esdhc
24 - fsl,t1040-esdhc
25 - fsl,t4240-esdhc
26 - fsl,ls1012a-esdhc
27 - fsl,ls1028a-esdhc
[all …]
H A Dfsl-imx-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
7 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
10 - compatible : Should be "fsl,<chip>-esdhc", the supported chips include
11 "fsl,imx25-esdhc"
12 "fsl,imx35-esdhc"
13 "fsl,imx51-esdhc"
14 "fsl,imx53-esdhc"
33 due to signal path is too long on the board. Please refer to eSDHC/uSDHC
54 esdhc@70004000 {
55 compatible = "fsl,imx51-esdhc";
[all …]
H A Dfsl-imx-esdhc.yaml4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
28 - fsl,imx51-esdhc
29 - fsl,imx53-esdhc
39 - const: fsl,imx50-esdhc
40 - const: fsl,imx53-esdhc
115 because the signal path is too long on the board. Please refer to eSDHC/uSDHC
[all …]
/freebsd/sys/dts/arm/
H A Dimx53x.dtsi217 /* 50004000 0x4000 ESDHC 1 */
218 esdhc@50004000 {
219 compatible = "fsl,imx53-esdhc";
225 /* 50008000 0x4000 ESDHC 2 */
226 esdhc@50008000 {
227 compatible = "fsl,imx53-esdhc";
262 /* 50020000 0x4000 ESDHC 3 */
263 esdhc@50020000 {
264 compatible = "fsl,imx53-esdhc";
271 /* 50024000 0x4000 ESDHC 4 */
[all …]
H A Dimx51x.dtsi178 /* 70004000 0x4000 ESDHC 1 */
179 esdhc@70004000 {
180 compatible = "fsl,imx51-esdhc";
186 /* 70008000 0x4000 ESDHC 2 */
187 esdhc@70008000 {
188 compatible = "fsl,imx51-esdhc";
220 /* 70020000 0x4000 ESDHC 3 */
221 esdhc@70020000 {
222 compatible = "fsl,imx51-esdhc";
228 /* 70024000 0x4000 ESDHC 4 */
[all …]
H A Defikamx.dts52 esdhc@70004000 {
56 esdhc@70008000 {
H A Ddigi-ccwmx53.dts58 esdhc@50004000 {
62 esdhc@50008000 {
/freebsd/sys/dev/sdhci/
H A Dfsl_sdhci.c31 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs).
161 * The clock enable bits exist in different registers for ESDHC vs USDHC, but
179 {"fsl,imx53-esdhc", HWTYPE_ESDHC},
180 {"fsl,imx51-esdhc", HWTYPE_ESDHC},
181 {"fsl,esdhc", HWTYPE_ESDHC},
280 * The ESDHC hardware has the typical 32-bit combined "command in fsl_sdhci_read_2()
427 * that can handle the ESDHC versus USDHC differences. in fsl_sdhci_write_2()
465 * just write them there and we're done. The ESDHC hardware has the in fsl_sdhci_write_2()
545 * On i.MX ESDHC hardware the card bus clock enable is in the usual in fsl_sdhc_get_clock()
548 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but in fsl_sdhc_get_clock()
[all …]
H A Dsdhci_fsl_fdt.c29 /* eSDHC controller driver for NXP QorIQ Layerscape SoCs. */
250 {"fsl,ls1012a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1012a_soc_data},
251 {"fsl,ls1028a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1028a_soc_data},
252 {"fsl,ls1046a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1046a_soc_data},
253 {"fsl,esdhc", (uintptr_t)&sdhci_fsl_fdt_gen_data},
421 * eSDHC hardware manages only a single slot. in sdhci_fsl_fdt_read_2()
519 * eSDHC hardware combines command and mode into a single in sdhci_fsl_fdt_write_2()
561 * eSDHC hardware lacks support for the SDMA buffer boundary in sdhci_fsl_fdt_write_4()
935 /* Figure out eSDHC block endianness before we touch any HW regs. */ in sdhci_fsl_fdt_attach()
954 * If the eSDHC block is connected over a big-endian bus, the data in sdhci_fsl_fdt_attach()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx50.dtsi119 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
131 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
180 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
192 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
H A Dimx35.dtsi235 compatible = "fsl,imx35-esdhc";
244 compatible = "fsl,imx35-esdhc";
253 compatible = "fsl,imx35-esdhc";
H A Dimx51.dtsi192 compatible = "fsl,imx51-esdhc";
203 compatible = "fsl,imx51-esdhc";
254 compatible = "fsl,imx51-esdhc";
266 compatible = "fsl,imx51-esdhc";
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dpq3-esdhc-0.dtsi2 * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
36 compatible = "fsl,esdhc";
H A Dqoriq-esdhc-0.dtsi2 * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
36 compatible = "fsl,esdhc";
H A Dc293si-post.dtsi113 /include/ "pq3-esdhc-0.dtsi"
115 compatible = "fsl,c293-esdhc", "fsl,esdhc";
H A Dp1020si-post.dtsi154 /include/ "pq3-esdhc-0.dtsi"
156 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
H A Dp1010si-post.dtsi172 /include/ "pq3-esdhc-0.dtsi"
174 compatible = "fsl,p1010-esdhc", "fsl,esdhc";
H A Dp2020si-post.dtsi202 /include/ "pq3-esdhc-0.dtsi"
204 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
H A Dp1022si-post.dtsi215 /include/ "pq3-esdhc-0.dtsi"
217 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
H A Dmpc8536si-post.dtsi243 /include/ "pq3-esdhc-0.dtsi"
245 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
H A Dmvme2500.dts270 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1012a.dtsi160 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
178 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
H A Dfsl-ls1028a-kontron-sl28.dts27 mmc1 = &esdhc;
100 &esdhc {
H A Dfsl-ls1028a-rdb.dts22 mmc0 = &esdhc;
161 &esdhc {

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