Searched +full:erratum +full:- +full:unknown1 (Results  1 – 4 of 4) sorted by relevance
| /linux/Documentation/devicetree/bindings/timer/ | 
| H A D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.03 ---
 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
 10   - Marc Zyngier <marc.zyngier@arm.com>
 11   - Mark Rutland <mark.rutland@arm.com>
 13   ARM cores may have a per-core architected timer, which provides per-cpu timers,
 17   The per-core architected timer is attached to a GIC to deliver its
 18   per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
 24       - items:
 25           - const: arm,cortex-a15-timer
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| /linux/drivers/clocksource/ | 
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only60 	bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
 64 	  Enables the support for the TI dual-mode timer driver.
 198 	  Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
 221 	  32-bit free running decrementing counters.
 256 	bool "Integrator-AP timer driver" if COMPILE_TEST
 259 	  Enables support for the Integrator-AP timer.
 284 	  available on many OMAP-like platforms.
 303 	bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
 307 	  These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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| H A D | arm_arch_timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only29 #include <linux/arm-smccc.h>
 47 	[ARCH_TIMER_PHYS_SECURE_PPI]	= "sec-phys",
 50 	[ARCH_TIMER_HYP_PPI]		= "hyp-phys",
 51 	[ARCH_TIMER_HYP_VIRT_PPI]	= "hyp-virt",
 78  *   2) a roll-over time of not less than 40 years
 87 	return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64);  in arch_counter_get_width()
 180 		_retries--;				\
 203  * Theoretically the erratum should not occur more than twice in succession
 216 		_retries--;					\
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| /linux/Documentation/arch/arm64/ | 
| H A D | silicon-errata.rst | 10 so-called "errata", which can cause it to deviate from the architecture30 a Category A erratum into a Category C erratum. These are collectively
 32 cases (e.g. those cases that both require a non-secure workaround *and*
 36 the erratum in question, a Kconfig entry is added under "Kernel
 37 Features" -> "ARM errata workarounds via the alternatives framework".
 40 detected. For less-intrusive workarounds, a Kconfig option is not
 42 a way that the erratum will not be hit.
 50 +----------------+-----------------+-----------------+-----------------------------+
 51 | Implementor    | Component       | Erratum ID      | Kconfig                     |
 53 | Allwinner      | A64/R18         | UNKNOWN1        | SUN50I_ERRATUM_UNKNOWN1     |
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