Searched +full:erratum +full:- +full:unknown1 (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Marc Zyngier <marc.zyngier@arm.com>11 - Mark Rutland <mark.rutland@arm.com>13 ARM cores may have a per-core architected timer, which provides per-cpu timers,17 The per-core architected timer is attached to a GIC to deliver its18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC24 - items:25 - const: arm,cortex-a15-timer[all …]
1 // SPDX-License-Identifier: GPL-2.0-only29 #include <linux/arm-smccc.h>47 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",50 [ARCH_TIMER_HYP_PPI] = "hyp-phys",51 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",78 * 2) a roll-over time of not less than 40 years87 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64); in arch_counter_get_width()180 _retries--; \203 * Theoretically the erratum should not occur more than twice in succession216 _retries--; \[all …]