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/freebsd/sys/dev/isci/scil/
H A Dscu_bios_definitions.h302 * These are the per PHY equalization settings associated with the
303 * AFE XCVR Tx Amplitude and Equalization Control Register Set
310 * - Software sets AFE XCVR Tx Control Register Tx Equalization
315 * LUTSel=00b. It contains the Tx Equalization settings that will be
322 * LUTSel=01b. It contains the Tx Equalization settings that will
329 * LUTSel=10b. It contains the Tx Equalization settings that will
336 * LUTSel=11b. It contains the Tx Equalization settings that will
499 * These are the per PHY equalization settings associated with the
500 * AFE XCVR Tx Amplitude and Equalization Control Register Set
507 * - Software sets AFE XCVR Tx Control Register Tx Equalization
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H A Dscic_sds_controller.c863 // Configure transmitter equalization in scic_sds_controller_afe_initialization()
961 // Configure transmitter equalization in scic_sds_controller_afe_initialization()
1064 // PM Rx Equalization Save, PM SPhy Rx Acknowledgement Timer, PM Stagger Timer in scic_sds_controller_afe_initialization()
1265 // Enable TX equalization (0xe824) in scic_sds_controller_afe_initialization()
1323 // Enable TX equalization (0xe824) in scic_sds_controller_afe_initialization()
1337 // Enable TX equalization (0xe824) in scic_sds_controller_afe_initialization()
1361 // Enable TX equalization (0xe824) in scic_sds_controller_afe_initialization()
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_hssp_internal_regs.h259 * Adaptive RX Equalization enable
260 * 0 - Disables adaptive RX equalization.
261 * 1 - Enables adaptive RX equalization.
308 * PHY Adaptive Equalization status
309 * 0 - Indicates Adaptive Equalization results are not valid for sampling
310 * 1 - Indicates Adaptive Equalization is complete and results are valid for
318 * PHY Adaptive Equalization Status Signal
319 * 0 – Indicates adaptive equalization results
321 * 1 – Indicates adaptive equalization is
H A Dal_hal_serdes_internal_regs.h260 * Adaptive RX Equalization enable
261 * 0 - Disables adaptive RX equalization.
262 * 1 - Enables adaptive RX equalization.
309 * PHY Adaptive Equalization status
310 * 0 - Indicates Adaptive Equalization results are not valid for sampling
311 * 1 - Indicates Adaptive Equalization is complete and results are valid for
319 * PHY Adaptive Equalization Status Signal
320 * 0 – Indicates adaptive equalization results
322 * 1 – Indicates adaptive equalization is
H A Dal_hal_serdes_interface.h233 * When set to false the values will be taken based in the equalization
334 * adaptive equalization */
813 * performs SerDes HW equalization test and update equalization parameters
820 * performs Rx equalization and compute the width and height of the eye
H A Dal_hal_pcie.h351 /** PCIe gen 3 standard per lane equalization parameters */
359 /** PCIe gen 3 equalization parameters */
366 al_bool eq_disable; /* disables the equalization feature */
367 al_bool eq_phase2_3_disable; /* Equalization Phase 2 and Phase 3 */
369 uint8_t local_lf; /* Full Swing (FS) Value for Gen3 Transmit Equalization */
372 uint8_t local_fs; /* Low Frequency (LF) Value for Gen3 Transmit Equalization */
1387 * Gen3 equalization must be disabled before enabling this mode
H A Dal_hal_pcie_interrupts.h165 /** [EP only] Link Equalization Request bit in the Link Status 2 Register has been set */
H A Dal_hal_pcie_w_reg.h759 /* Decode of the Recovery. Equalization LTSSM state */
1287 * Notification that the Link Equalization Request bit in the Link Status 2
H A Dal_hal_serdes_25g.c1075 al_err("%s: Failed to run equalization\n", __func__); in al_serdes_25g_rx_equalization()
/freebsd/sys/dev/al_eth/
H A Dal_init_eth_lm.h236 * - if rx_equal is set serdes equalization will be run to configure the rx parameters.
305 * run LT, rx equalization and static values override according to configuration
H A Dal_init_eth_lm.c601 al_warn("serdes rx equalization failed on error\n"); in al_eth_rx_equal_run()
634 al_warn("serdes rx equalization failed on error\n"); in al_eth_rx_equal_run()
1421 lm_debug("%s: link is up with Rx Equalization\n", __func__); in al_eth_lm_link_establish()
H A Dal_init_eth_kr.c804 * the link training progress will run rx equalization so need to make in al_eth_an_lt_execute()
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dbaikal,bt1-pcie.yaml42 MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization
H A Dsnps,dw-pcie-ep.yaml130 Link Equalization Request flag is set in the Link Status 2
H A Dsnps,dw-pcie.yaml139 Link Equalization Request flag is set in the Link Status 2
H A Dsnps,dw-pcie-common.yaml52 bandwidth change, link equalization request, INTx asserted/deasserted
/freebsd/contrib/ofed/opensm/include/opensm/
H A Dosm_port_profile.h110 * equalization algorithm.
H A Dosm_port.h180 * the link load equalization algorithm.
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dcirrus,cs35l41.yaml14 speaker protection and equalization
/freebsd/sys/dev/sfxge/common/
H A Defx_regs_pci.h1427 * Lanes 0,1 Equalization Control Register.
1482 * Lanes 2,3 Equalization Control Register.
1523 * Lanes 4,5 Equalization Control Register.
1550 * Lanes 6,7 Equalization Control Register.
/freebsd/contrib/ofed/opensm/man/
H A Dopensm.8304 equalization algorithm.
901 avoids port equalization except for redundant links between the same
995 equalization algorithm. Note that only endports (CA,
1244 unless port equalization is turned off. In the case of hypercubes,
/freebsd/sys/dev/ice/
H A Dice_lib.h632 * @brief serdes equalization info
667 struct ice_serdes_equalization equalization[ICE_MAX_SERDES_LANE_COUNT]; member
/freebsd/contrib/ofed/opensm/opensm/
H A Dosm_ucast_mgr.c283 we would like to optionally ignore this port in equalization in ucast_mgr_process_port()
H A Dmain.c295 " equalization algorithm.\n\n"); in show_usage()
/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h1070 … (0x1<<17) // Equalization complete.
1072 … (0x1<<18) // Equalization phase 1 success…
1074 … (0x1<<19) // Equalization phase 2 success…
1076 … (0x1<<20) // Equalization phase 3 success…
1078 … (0x1<<21) // Link equalization request.
1109 …PCIE_CAP_EQ_CPL_K2 (0x1<<17) // Equalization 8.0GT/s Complet…
1111 …PCIE_CAP_EQ_CPL_P1_K2 (0x1<<18) // Equalization 8.0GT/s Phase 1…
1113 …PCIE_CAP_EQ_CPL_P2_K2 (0x1<<19) // Equalization 8.0GT/s Phase 2…
1115 …PCIE_CAP_EQ_CPL_P3_K2 (0x1<<20) // Equalization 8.0GT/s Phase 3…
1117 …CAP_LINK_EQ_REQ_K2 (0x1<<21) // Link Equalization Request 8.0GT/s.
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