| /linux/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/ |
| H A D | ali_drw.json | 171 "BriefDescription": "Rank0 enters self-refresh(SRE).",
178 "BriefDescription": "Rank1 enters self-refresh(SRE).",
185 "BriefDescription": "Rank2 enters self-refresh(SRE).",
192 "BriefDescription": "Rank3 enters self-refresh(SRE).",
199 "BriefDescription": "Rank0 enters power-down(PDE).",
206 "BriefDescription": "Rank1 enters power-down(PDE).",
213 "BriefDescription": "Rank2 enters power-down(PDE).",
220 "BriefDescription": "Rank3 enters power-down(PDE).",
|
| /linux/include/trace/events/ |
| H A D | context_tracking.h | 42 * user_exit - called when userspace enters the kernel
45 * This event occurs when userspace enters the kernel through
|
| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | frontend.json | 20 …"BriefDescription": "Counts every time the code stream enters into a new cache line by walking seq…
28 …"BriefDescription": "Counts every time the code stream enters into a new cache line by walking seq…
|
| /linux/Documentation/arch/x86/ |
| H A D | mds.rst | 22 not possible. But if a thread enters or exits a sleep state the store
92 enters a C-state.
173 When a CPU goes idle and enters a C-State the CPU buffers need to be
175 repartitioning of the store buffer when one of the Hyper-Threads enters
|
| /linux/Documentation/block/ |
| H A D | deadline-iosched.rst | 21 tunable. When a read request first enters the io scheduler, it is assigned
60 Sometimes it happens that a request enters the io scheduler that is contiguous
|
| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | frontend.json | 84 …"BriefDescription": "Counts every time the code stream enters into a new cache line by walking seq…
92 …"BriefDescription": "Counts every time the code stream enters into a new cache line by walking seq…
|
| /linux/drivers/net/wireless/ti/wl12xx/ |
| H A D | acx.h | 141 /* the amount of enters into power save mode (both PD & ELP) */
144 /* the amount of enters into ELP mode */
|
| /linux/drivers/target/ |
| H A D | target_core_ua.c | 53 * a) if an INQUIRY command enters the enabled command state, the in target_scsi3_ua_check()
56 * b) if a REPORT LUNS command enters the enabled command state, the in target_scsi3_ua_check()
59 * e) if a REQUEST SENSE command enters the enabled command state while in target_scsi3_ua_check()
|
| /linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | pipeline.json | 300 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
309 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
325 "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
334 "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
342 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
351 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
|
| /linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | pipeline.json | 162 …he number of core cycles while the core is not in a halt state. The core enters the halt state whe…
171 …he number of core cycles while the core is not in a halt state. The core enters the halt state whe…
179 …umber of reference cycles that the core is not in a halt state. The core enters the halt state whe…
187 …umber of reference cycles that the core is not in a halt state. The core enters the halt state whe…
196 …umber of reference cycles that the core is not in a halt state. The core enters the halt state whe…
|
| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | pipeline.json | 162 …he number of core cycles while the core is not in a halt state. The core enters the halt state whe…
171 …he number of core cycles while the core is not in a halt state. The core enters the halt state whe…
179 …umber of reference cycles that the core is not in a halt state. The core enters the halt state whe…
187 …umber of reference cycles that the core is not in a halt state. The core enters the halt state whe…
196 …umber of reference cycles that the core is not in a halt state. The core enters the halt state whe…
|
| /linux/Documentation/livepatch/ |
| H A D | livepatch.rst | 84 switch over. When a patch is enabled, livepatch enters into a
117 allows them to be patched before the CPU enters the idle state.
324 Second, livepatch enters into a transition state where tasks are converging
369 First, livepatch enters into a transition state where tasks are converging
|
| /linux/drivers/irqchip/ |
| H A D | exynos-combiner.c | 206 * the state is lost when the system enters into a sleep state.
225 * the state is lost when the system enters into a sleep state on suspend.
|
| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 164 …he number of core cycles while the core is not in a halt state. The core enters the halt state whe…
173 …he number of core cycles while the core is not in a halt state. The core enters the halt state whe…
181 …umber of reference cycles that the core is not in a halt state. The core enters the halt state whe…
189 …mber of reference cycles while the core is not in a halt state. The core enters the halt state whe…
|
| /linux/arch/xtensa/include/asm/ |
| H A D | dma.h | 43 * enters another area, and virt_to_phys() may not return
|
| /linux/arch/arm/include/asm/ |
| H A D | firmware.h | 26 * Enters CPU idle mode
|
| /linux/Documentation/ABI/testing/ |
| H A D | debugfs-pcie-ptm | 63 invalidated by hardware if the Root Complex enters low power
|
| /linux/arch/arm/mach-tegra/ |
| H A D | sleep-tegra20.S | 140 * Enters suspend in LP0 or LP1 by turning off the mmu and jumping to
165 * Switches the CPU cluster to PLL-P and enters sleep.
|
| /linux/tools/testing/selftests/kvm/ |
| H A D | rseq_test.c | 113 * ioctl(KVM_RUN) enters the guest so that TIF_NOTIFY_RESUME in migration_worker()
117 * If NOTIFY_RESUME/NEED_RESCHED is set after KVM enters in migration_worker()
|
| /linux/Documentation/devicetree/bindings/power/supply/ |
| H A D | mediatek,mt6370-charger.yaml | 29 hardware enters the "Minimum Input Voltage Regulation loop" and
|
| /linux/Documentation/networking/devlink/ |
| H A D | netdevsim.rst | 97 - When a packet enters the device it is classified to a filtering
|
| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | pipeline.json | 597 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
607 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
675 "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
684 "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
694 "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
704 "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
713 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
722 "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
732 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
741 "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters th
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | frontend.json | 555 "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
564 "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
573 "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are present.",
582 "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
591 "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
|
| /linux/tools/power/cpupower/man/ |
| H A D | cpupower-idle-info.1 | 26 statistics when it enters or leaves an idle state, therefore on a very idle or
|
| /linux/tools/include/uapi/linux/ |
| H A D | tcp.h | 187 * The sender enters disordered state when it has received DUPACKs or
195 * The sender enters Congestion Window Reduction (CWR) state when it
|