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/freebsd/sys/contrib/device-tree/src/arm64/cavium/
H A Dthunder-88xx.dtsi2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
58 method = "smc";
62 #address-cells = <2>;
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/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A Delba-16core.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2023 Advanced Micro Devices, Inc.
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu-map {
44 compatible = "arm,cortex-a72";
46 next-level-cache = <&l2_0>;
47 enable-method = "psci";
52 compatible = "arm,cortex-a72";
54 next-level-cache = <&l2_0>;
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H A Damd-seattle-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #address-cells = <0x1>;
6 #size-cells = <0x0>;
8 cpu-map {
45 compatible = "arm,cortex-a57";
47 enable-method = "psci";
49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <256>;
52 d-cache-size = <0x8000>;
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 1 - Introduction
18 where cores can be put in different low-power states (ranging from simple wfi
20 range of dynamic idle states that a processor can enter at run-time, can be
27 - Running
28 - Idle_standby
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/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-ap810-ap0-octa-core.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap810-ap0.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 compatible = "marvell,armada-ap810-octa";
18 compatible = "arm,cortex-a72";
20 enable-method = "psci";
24 compatible = "arm,cortex-a72";
26 enable-method = "psci";
30 compatible = "arm,cortex-a72";
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/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
18 method = "smc";
22 #address-cells = <1>;
23 #size-cells = <0>;
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H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
18 method = "smc";
22 #address-cells = <1>;
23 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6755.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&sysirq>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
18 method = "smc";
22 #address-cells = <1>;
23 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/Bindings/
H A Dnuma.txt6 1 - Introduction
18 2 - numa-node-id
23 a node id is a 32-bit integer.
26 numa-node-id property which contains the node id of the device.
30 numa-node-id = <0>;
33 numa-node-id = <1>;
36 3 - distance-map
39 The optional device tree node distance-map describes the relative
42 - compatible : Should at least contain "numa-distance-map-v1".
44 - distance-matrix
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/freebsd/sys/contrib/device-tree/src/arm64/amazon/
H A Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Damlogic-t7.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/amlogic,t7-pwrc.h>
8 #include "amlogic-t7-reset.h"
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <0x2>;
17 #size-cells = <0x0>;
19 cpu-map {
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H A Dmeson-g12b.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12.dtsi"
13 #address-cells = <0x2>;
14 #size-cells = <0x0>;
16 cpu-map {
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 capacity-dmips-mhz = <592>;
52 next-level-cache = <&l2>;
53 #cooling-cells = <2>;
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/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynosautov920.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov920.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,exynos-usi.h>
15 #address-cells = <2>;
16 #size-cells = <1>;
18 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a78-pmu";
37 compatible = "fixed-clock";
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/freebsd/sys/contrib/device-tree/Bindings/arm/cpu-enable-method/
H A Dmarvell,berlin-smp2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
15 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16 "marvell,berlin-cpu-ctrl"[1].
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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H A Dal,alpine-smp2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
16 This enable method requires valid nodes compatible with
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set for the device
33 #address-cells = <1>;
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H A Dnuvoton,npcm750-smp2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Ds32g3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2021-2024 NXP
7 * Andra-Teodora Ilie <andra.ilie@nxp.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu-map {
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/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-qcom-hw.txt8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
18 - clock-names
23 - reg
25 Value type: <prop-encoded-array>
28 - reg-names
32 "freq-domain0", "freq-domain1".
34 - #freq-domain-cells:
38 * Property qcom,freq-domain
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/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dfoundation-v8-psci.dtsi9 compatible = "arm,psci-1.0";
10 method = "smc";
15 enable-method = "psci";
19 enable-method = "psci";
23 enable-method = "psci";
27 enable-method = "psci";
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-topology.txt6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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/freebsd/sys/contrib/device-tree/src/arm64/sprd/
H A Dums9620.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
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/freebsd/sys/dev/isci/scil/
H A Dsci_logger.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
73 /* The following is a list of verbosity levels that can be used to enable */
76 /** Enable/disable error level logging for the associated logger object(s). */
79 /** Enable/disable warning level logging for the associated logger object(s). */
83 * Enable/disable informative level logging for the associated logger object(s).
88 * This constant is used to enable function trace (enter/exit) level
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/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-msm8916-smp.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 enable-method = "qcom,msm8916-smp";
9 enable-method = "qcom,msm8916-smp";
12 enable-method = "qcom,msm8916-smp";
15 enable-method = "qcom,msm8916-smp";
18 idle-states {
19 /delete-property/ entry-method;
29 compatible = "qcom,idle-state-spc", "arm,idle-state";
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210-p2530.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 stdout-path = "serial0:115200n8";
24 /delete-property/ dmas;
25 /delete-property/ dma-names;
31 clock-frequency = <400000>;
35 nvidia,invert-interrupt;
41 bus-widt
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