Searched +full:enable +full:- +full:hs +full:- +full:rx +full:- +full:gain +full:- +full:eq (Results 1 – 6 of 6) sorted by relevance
6 # http://www.linux-usb.org/usb-ids.html7 # or send entries as patches (diff -u old new) in the10 # http://www.linux-usb.org/usb.ids13 # Date: 2025-04-01 20:34:0220 # device device_name <-- single tab21 # interface interface_name <-- two tabs38 5301 GW-US54ZGL 802.11bg54 145f NW-3100 802.11b/g 54Mbps Wireless Network Adapter [zd1211]62 0200 TP-Link81 120e ASI120MC-S Planetary Camera[all …]
9 * or http://opensource.org/licenses/CDDL-1.0.23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.079 …c mask enable Bit5 : Mask Message VDM Bit4 : Mask memory read Bit3 : Mask memory write Bit2 : …80 … 0x00381cUL //Access:R DataWidth:0x20 // Number of RX tlp are received81 … 0x003820UL //Access:R DataWidth:0x20 // Byte number of RX are received84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…86 …R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync …87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…[all …]
9 * or http://opensource.org/licenses/CDDL-1.0.23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.080 …c mask enable Bit5 : Mask Message VDM Bit4 : Mask memory read Bit3 : Mask memory write Bit2 : …81 … 0x00381cUL //Access:R DataWidth:0x20 // Number of RX tlp are received82 … 0x003820UL //Access:R DataWidth:0x20 // Byte number of RX are received85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…87 …R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync …88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…[all …]
9 * or http://opensource.org/licenses/CDDL-1.0.23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.079 …c mask enable Bit5 : Mask Message VDM Bit4 : Mask memory read Bit3 : Mask memory write Bit2 : …80 … 0x00381cUL //Access:R DataWidth:0x20 Number of RX tlp are received C…81 … 0x003820UL //Access:R DataWidth:0x20 Byte number of RX are received Chips:…85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…[all …]