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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 USB HS PHY controller
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
42 "#address-cells":
45 "#size-cells":
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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp135f-dhcor-dhsbc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
7 * DHCOR PCB number: 718-100 or newer
8 * DHSBC PCB number: 719-100 or newer
11 /dts-v1/;
13 #include <dt-bindings/regulator/st,stm32mp13-regulator.h>
16 #include "stm32mp13xx-dhcor-som.dtsi"
20 compatible = "dh,stm32mp135f-dhcor-dhsbc",
21 "dh,stm32mp135f-dhcor-som",
32 stdout-path = "serial0:115200n8";
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H A Dstm32mp135f-dk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/st,stm32mp13-regulator.h>
15 #include "stm32mp13-pinctrl.dtsi"
18 model = "STMicroelectronics STM32MP135F-DK Discovery Board";
19 compatible = "st,stm32mp135f-dk", "st,stm32mp135";
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/freebsd/share/misc/
H A Dusb_vendors6 # http://www.linux-usb.org/usb-ids.html
7 # or send entries as patches (diff -u old new) in the
10 # http://www.linux-usb.org/usb.ids
13 # Date: 2025-07-26 20:34:01
20 # device device_name <-- single tab
21 # interface interface_name <-- two tabs
38 5301 GW-US54ZGL 802.11bg
54 145f NW-3100 802.11b/g 54Mbps Wireless Network Adapter [zd1211]
64 0200 TP-Link
86 120e ASI120MC-S Planetary Camera
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
73 …c mask enable Bit5 : Mask Message VDM Bit4 : Mask memory read Bit3 : Mask memory write Bit2 : …
74 … 0x00381cUL //Access:R DataWidth:0x20 // Number of RX tlp are received
75 … 0x003820UL //Access:R DataWidth:0x20 // Byte number of RX are received
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync …
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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