| /linux/drivers/spi/ |
| H A D | spi-ppc4xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
55 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
69 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
101 * SCPClkOut = OPBCLK/(4(CDM + 1))
103 * CDM = (OPBCLK/4*SCPClkOut) - 1
106 u8 cdm; member
143 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", in spi_ppc4xx_txrx()
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| /linux/arch/powerpc/platforms/52xx/ |
| H A D | mpc52xx_common.c | 25 { .compatible = "fsl,mpc5200-xlb", },
26 { .compatible = "mpc5200-xlb", },
30 { .compatible = "fsl,mpc5200-immr", },
31 { .compatible = "fsl,mpc5200b-immr", },
32 { .compatible = "simple-bus", },
71 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
72 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
77 * transaction and re-enable it afterwards ...) in mpc5200_setup_xlb_arbiter()
81 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); in mpc5200_setup_xlb_arbiter()
110 { .compatible = "fsl,mpc5200-gpt", },
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | rcar-gen4-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Renesas Electronics Corp.
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Gen4 PCIe Host
11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 - $ref: snps,dw-pcie.yaml#
19 - enum:
20 - renesas,r8a779f0-pcie # R-Car S4-8
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_kms.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
13 #include <linux/dma-buf.h>
44 * To enable overall DRM driver logging
47 * To enable DRM driver h/w logging
66 struct dpu_kms *kms = s->private; in _dpu_danger_signal_status()
69 if (!kms->hw_mdp) { in _dpu_danger_signal_status()
76 pm_runtime_get_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
79 if (kms->hw_mdp->ops.get_danger_status) in _dpu_danger_signal_status()
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| H A D | dpu_encoder_phys_vid.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
18 (e) && (e)->parent ? \
19 (e)->parent->base.id : -1, \
20 (e) && (e)->hw_intf ? \
21 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
24 (e) && (e)->parent ? \
25 (e)->parent->base.id : -1, \
26 (e) && (e)->hw_intf ? \
27 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
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| H A D | dpu_encoder.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
40 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
43 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
46 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
67 * enum dpu_enc_rc_events - events for resource control state machine
71 * received, enable MDP/DSI core clocks. Regardless of the previous
106 * enum dpu_enc_rc_states - states that the resource control maintains
121 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
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| /linux/drivers/pci/controller/dwc/ |
| H A D | pcie-tegra194.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
295 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
300 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
305 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
308 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_bas in tegra_pcie_icc_set()
1212 tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw * pcie,bool enable) tegra_pcie_bpmp_set_ctrl_state() argument
1250 tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw * pcie,bool enable) tegra_pcie_bpmp_set_pll_state() argument
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| H A D | pcie-designware.c | 1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/pcie-dwc.h>
26 #include "pcie-designware.h"
48 [DW_PCIE_NON_STICKY_RST] = "non-sticky",
70 pci->app_clks[i].id = dw_pcie_app_clks[i]; in dw_pcie_get_clocks()
73 pci->core_clks[i].id = dw_pcie_core_clks[i]; in dw_pcie_get_clocks()
75 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, in dw_pcie_get_clocks()
76 pci->app_clk in dw_pcie_get_clocks()
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| /linux/drivers/gpu/drm/imagination/ |
| H A D | pvr_rogue_fwif_sf.h | 1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
47 * - --- ---- ---- ---- ---- ---- ---- ----
48 * 0-11: id number
49 * 12-15: group id number
50 * 16-19: number of parameters
51 * 20-27: unused
52 * 28-30: active: identify SF packet, otherwise regular int32
110 "UFO Check: [0x%08.8x] is 0x%08.8x requires 0x%08.8x" },
114 "UFO PR-Check: [0x%08.8x] is 0x%08.8x requires >= 0x%08.8x" },
116 "UFO SPM PR-Checks for FWCtx 0x%08.8x" },
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| H A D | pvr_rogue_fwif.h | 1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
42 /* String used in pvrdebug -h output */
140 /* Firmware per-DM HWR states */
155 /* DM was identified as over-running and causing HWR */
157 /* DM was innocently affected by another DM over-running which caused HWR */
270 /* Identify whether MC config is P-P or P-S */
274 /* per-os firmware shared data */
278 /* Markers to signal that the host should perform a full sync check */
297 /* Firmware trace time-stamp field breakup */
303 /* Extra debug-info (16 bits) */
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r8a779f0.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
18 cluster01_opp: opp-table-0 {
19 compatible = "operating-points-v2";
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| H A D | r8a779g0.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4H (R8A779G0) SoC
8 #include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779g0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
18 /* External Audio clock - to be overridden by boards that provide it */
20 compatible = "fixed-clock";
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| H A D | r8a779h0.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4M (R8A779H0) SoC
8 #include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/renesas,r8a779h0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
18 /* External Audio clock - to be overridden by boards that provide it */
20 compatible = "fixed-clock";
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| /linux/drivers/net/ethernet/mediatek/ |
| H A D | mtk_eth_soc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
35 static int mtk_msg_level = -1;
37 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
291 __raw_writel(val, eth->base + reg); in mtk_w32()
296 return __raw_readl(eth->base + reg); in mtk_r32()
322 dev_err(eth->dev, "mdio: MDIO timeout\n"); in mtk_mdio_busy_wait()
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