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Searched +full:emc +full:- +full:timings +full:- +full:3 (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/memory/tegra/
H A Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
55 #define EMC1_EMC_DATA_BRLSHFT_0_INDEX 3
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
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H A Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
180 #define EMC_CFG5_QUSE_MODE_PULSE_INTERN 3
215 #define EMC_REFRESH_OVERFLOW_INT BIT(3)
242 [3] = EMC_RP,
366 struct emc_timing *timings; member
387 * There are multiple sources in the EMC driver which could request
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H A Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/interconnect-provider.h>
101 #define EMC_REFRESH_OVERFLOW_INT BIT(3)
122 #define EMC_PWR_GATHER_ENABLE (3 << 8)
206 struct emc_timing *timings; member
216 * There are multiple sources in the EMC driver which could request
221 /* protect shared rate-change code path */
237 struct tegra_emc *emc = data; in tegra_emc_isr() local
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
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H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
204 #define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3)
269 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3)
291 DRAM_TYPE_DDR2 = 3
495 struct emc_timing *timings; member
507 * There are multiple sources in the EMC driver which could request
512 /* protect shared rate-change code path */
518 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
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H A Dtegra210-emc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
144 #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC BIT(3)
191 #define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN BIT(3)
264 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3
290 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3
673 #define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR BIT(3)
675 #define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR BIT(3)
884 #define DRAM_TYPE_DDR2 3
891 /* nominal EMC frequency table */
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H A Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
18 #include <linux/tegra-icc.h>
26 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
29 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
32 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
35 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
38 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
41 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
44 { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
28 clock-names:
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H A Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
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/linux/drivers/clk/tegra/
H A Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
47 * List of clock sources for various parents the EMC clock can have.
56 #define EMC_SRC_CLK_M 3
79 struct tegra_emc *emc; member
82 struct emc_timing *timings; member
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
113 * safer since things have EMC rate floors. Also don't touch parent_rate
125 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
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H A Dclk-tegra210-emc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
25 #define CLK_SRC_CLK_M 3
53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate()
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf300tg.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
8 model = "Asus Transformer Pad 3G TF300TG";
12 tf300tg-init-hog {
13 gpio-hog;
18 <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>,
19 <TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>,
24 <TEGRA_GPIO(Y, 3) GPIO_ACTIVE_HIGH>,
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H A Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
52 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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H A Dtegra30-asus-tf300t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300t-init-hog {
13 gpio-hog;
15 output-low;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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H A Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
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H A Dtegra30-lg-p895.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
11 pinctrl-names = "default";
12 pinctrl-0 = <&state_default>;
15 /* GNSS UART-B pinmux */
16 uartb-cts-rxd {
22 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
24 uartb-rts-txd {
30 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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H A Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-3 {
8 nvidia,ram-code = <3>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
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H A Dtegra30-ouya.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
26 stdout-path = "serial0:115200n8";
30 trusted-foundations {
31 compatible = "tlm,trusted-foundations";
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H A Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
16 chassis-type = "convertible";
33 * pre-existing /chosen node to be available to insert the
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