/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
H A D | nvidia,tegra20-emc.txt | 4 - name : Should be emc 5 - #address-cells : Should be 1 6 - #size-cells : Should be 0 7 - compatible : Should contain "nvidia,tegra20-emc". 8 - reg : Offset and length of the register set for the device 9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed 12 irrespective of ram-code configuration. 13 - interrupts : Should contain EMC General interrupt. 14 - clocks : Should contain EMC clock. 15 - nvidia,memory-controller : Phandle of the Memory Controller node. [all …]
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H A D | nvidia,tegra20-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dmitry Osipenko <digetx@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Thierry Reding <thierry.reding@gmail.com> 15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to 16 service the request stream sent from Memory Controller. The EMC also has 17 various performance-affecting settings beyond the obvious SDRAM configuration [all …]
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H A D | nvidia,tegra210-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The EMC interfaces with the off-chip SDRAM to service the request stream 19 const: nvidia,tegra210-emc 26 - description: external memory clock 28 clock-names: [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/ |
H A D | tegra20-acer-a500-picasso.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/atmel-maxtouch.h> 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/input/input.h> 7 #include <dt-binding [all...] |
H A D | tegra20-paz00.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 5 #include <dt-bindings/thermal/thermal.h> 8 #include "tegra20-cpu-opp.dtsi" 9 #include "tegra20-cpu-opp-microvolt.dtsi" 25 stdout-path = "serial0:115200n8"; 44 vdd-supply = <&hdmi_vdd_reg>; 45 pll-supply = <&hdmi_pll_reg>; 47 nvidia,ddc-i2c-bus = <&hdmi_ddc>; [all …]
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H A D | tegra20-colibri.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 22 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 23 nvidia,hpd-gpio = 25 pll-supply = <®_1v8_avdd_hdmi_pll>; 26 vdd-supply = <®_3v3_avdd_hdmi>; 31 lan-reset-n-hog { 32 gpio-hog; 34 output-high; 35 line-name = "LAN_RESET#"; 38 /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ [all …]
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H A D | tegra20-asus-tf101.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/atmel-maxtouch.h> 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/input/input.h> 7 #include <dt-binding [all...] |
H A D | tegra30-asus-tf201.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra30-asus-transformer-common.dtsi" 5 #include "tegra30-asus-lvds-display.dtsi" 19 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 27 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 35 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 43 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 51 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 57 /* Azurewave AW-NH615 BCM4329B1 */ [all …]
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H A D | tegra30-asus-tf700t.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra30-asus-transformer-common.dtsi" 20 remote-endpoint = <&bridge_input>; 21 bus-width = <24>; 36 nvidia,enable-inpu [all...] |
H A D | tegra124-nyan-blaze-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/tegra124-car.h> 7 emc-timings-1 { 8 nvidia,ram-code = <1>; 10 timing-12750000 { 11 clock-frequency = <12750000>; 12 nvidia,parent-clock-frequency = <408000000>; 14 clock-names = "emc-parent"; 17 timing-20400000 { 18 clock-frequency = <20400000>; [all …]
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H A D | tegra30-asus-tf300t.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra30-asus-transformer-common.dtsi" 5 #include "tegra30-asus-lvds-display.dtsi" 12 tf300t-init-hog { 13 gpio-hog; 15 output-low; 27 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 35 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 43 nvidia,enable-input = <TEGRA_PIN_ENABLE>; [all …]
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H A D | tegra124-apalis-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR X11 3 * Copyright 2016-2019 Toradex AG 7 #include <dt-bindings/clock/tegra124-car.h> 11 emc-timings-1 { 12 nvidia,ram-code = <1>; 14 timing-12750000 { 15 clock-frequency = <12750000>; 16 nvidia,parent-clock-frequency = <408000000>; 18 clock-names = "emc-parent"; 21 timing-20400000 { [all …]
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H A D | tegra124-jetson-tk1-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/tegra124-car.h> 7 emc-timings-3 { 8 nvidia,ram-code = <3>; 10 timing-12750000 { 11 clock-frequency = <12750000>; 12 nvidia,parent-clock-frequency = <408000000>; 14 clock-names = "emc-parent"; 17 timing-20400000 { 18 clock-frequency = <20400000>; [all …]
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H A D | tegra30-asus-tf300tg.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra30-asus-transformer-common.dtsi" 5 #include "tegra30-asus-lvds-display.dtsi" 12 tf300tg-init-hog { 13 gpio-hog; 28 output-low; 39 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 47 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 55 nvidia,enable-input = <TEGRA_PIN_ENABLE>; [all …]
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H A D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 memory-controller@7000f000 { 5 emc-timings-0 { 6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ 8 timing-25500000 { 9 clock-frequency = <25500000>; 11 nvidia,emem-configuration = < 33 timing-51000000 { 34 clock-frequency = <51000000>; 36 nvidia,emem-configuration = < [all …]
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H A D | tegra20-seaboard.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 18 stdout-path = "serial0:115200n8"; 37 vdd-supply = <&hdmi_vdd_reg>; 38 pll-supply = <&hdmi_pll_reg>; 39 hdmi-supply = <&vdd_hdmi>; 41 nvidia,ddc-i2 [all...] |
H A D | tegra30-pegatron-chagall.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/gpio-keys.h> 5 #include <dt-bindings/input/input.h> 6 #include <dt-bindings/thermal/thermal.h> 9 #include "tegra30-cpu-op [all...] |
H A D | tegra124-nyan-big-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/tegra124-car.h> 7 emc-timings-1 { 8 nvidia,ram-code = <1>; 10 timing-12750000 { 11 clock-frequency = <12750000>; 12 nvidia,parent-clock-frequency = <408000000>; 14 clock-names = "emc-parent"; 17 timing-20400000 { 18 clock-frequency = <20400000>; [all …]
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H A D | tegra30-ouya.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/gpio-keys.h> 5 #include <dt-bindings/input/input.h> 6 #include <dt-bindings/thermal/thermal.h> 9 #include "tegra30-cpu-op [all...] |
/freebsd/sys/contrib/device-tree/Bindings/reserved-memory/ |
H A D | nvidia,tegra210-emc-table.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra210-emc-table.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra210 EMC Frequency Table 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 EMC frequency table via a reserved memory region. 17 - $ref: reserved-memory.yaml 21 const: nvidia,tegra210-emc-table [all …]
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/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/ |
H A D | nvidia,tegra30-actmon.txt | 9 - compatible: should be "nvidia,tegra<chip>-actmon" 10 - reg: offset and length of the register set for the device 11 - interrupts: standard interrupt property 12 - clocks: Must contain a phandle and clock specifier pair for each entry in 13 clock-names. See ../../clock/clock-bindings.txt for details. 14 - clock-names: Must include the following entries: 15 - actmon 16 - emc 17 - resets: Must contain an entry for each entry in reset-names. See 19 - reset-names: Must include the following entries: [all …]
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/freebsd/tools/test/stress2/misc/ |
H A D | kpti.sh | 4 # SPDX-License-Identifier: BSD-2-Clause 6 # Copyright (c) 2019 Dell EMC Isilon 30 # Simple test of kpti (Kernel page-table isolation) enable / disable 35 [ `id -u ` -ne 0 ] && echo "Must be root!" && exit 1 36 proccontrol -m kpti -q 2> /dev/null || exit 0 37 [ `sysctl -n vm.pmap.pti` -eq 1 ] && echo "Page Table Isolation enabled" || 38 echo "Page Table Isolation disabled" 41 [ $# -eq 1 ] && prog=$1 43 while [ $((`date +%s` - start)) -lt 120 ]; do 45 proccontrol -m kpti -s disable $prog & [all …]
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/freebsd/sys/contrib/device-tree/Bindings/reset/ |
H A D | nxp,lpc1850-rgu.txt | 8 - compatible: Should be "nxp,lpc1850-rgu" 9 - reg: register base and length 10 - clocks: phandle and clock specifier to RGU clocks 11 - clock-names: should contain "delay" and "reg" 12 - #reset-cells: should be 1 14 See table below for valid peripheral reset numbers. Numbers not 15 in the table below are either reserved or not applicable for 20 12 ARM Cortex-M0 subsystem core (LPC43xx only) 27 21 External memory controller (EMC) 56 56 ARM Cortex-M0 application core (LPC4370 only) [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/ |
H A D | tegra132-peripherals-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 /* EMC DVFS OPP table */ 5 emc_icc_dvfs_opp_table: opp-table-dvfs0 { 6 compatible = "operating-points-v2"; 8 opp-12750000-800 { 9 opp-microvolt = <800000 800000 1150000>; 10 opp-hz = /bits/ 64 <12750000>; 11 opp-supported-hw = <0x0003>; 14 opp-12750000-950 { 15 opp-microvolt = <950000 950000 1150000>; [all …]
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/freebsd/contrib/telnet/telnet/ |
H A D | baud.h | 2 * Copyright (c) 2014 EMC Corporation 79 * A table of available terminal speeds 120 { -1, 0 }
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