/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra30-asus-tf300t.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra30-asus-transformer-common.dtsi" 5 #include "tegra30-asus-lvds-display.dtsi" 12 tf300t-init-hog { 13 gpio-hog; 15 output-low; 27 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 35 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 43 nvidia,enable-input = <TEGRA_PIN_ENABLE>; [all …]
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H A D | tegra30-asus-tf300tg.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra30-asus-transformer-common.dtsi" 5 #include "tegra30-asus-lvds-display.dtsi" 12 tf300tg-init-hog { 13 gpio-hog; 28 output-low; 39 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 47 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 55 nvidia,enable-input = <TEGRA_PIN_ENABLE>; [all …]
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H A D | tegra30-asus-tf700t.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra30-asus-transformer-common.dtsi" 20 remote-endpoint = <&bridge_input>; 21 bus-width = <24>; 36 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 44 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 52 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 60 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 68 nvidia,enable-input = <TEGRA_PIN_DISABLE>; [all …]
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H A D | tegra30-asus-tf201.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra30-asus-transformer-common.dtsi" 5 #include "tegra30-asus-lvds-display.dtsi" 19 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 27 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 35 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 43 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 51 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 57 /* Azurewave AW-NH615 BCM4329B1 */ [all …]
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H A D | tegra124-apalis-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR X11 3 * Copyright 2016-2019 Toradex AG 7 #include <dt-bindings/clock/tegra124-car.h> 11 emc-timings-1 { 12 nvidia,ram-code = <1>; 14 timing-12750000 { 15 clock-frequency = <12750000>; 16 nvidia,parent-clock-frequency = <408000000>; 18 clock-names = "emc-parent"; 21 timing-20400000 { [all …]
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H A D | tegra124-jetson-tk1-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/tegra124-car.h> 7 emc-timings-3 { 8 nvidia,ram-code = <3>; 10 timing-12750000 { 11 clock-frequency = <12750000>; 12 nvidia,parent-clock-frequency = <408000000>; 14 clock-names = "emc-parent"; 17 timing-20400000 { 18 clock-frequency = <20400000>; [all …]
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H A D | tegra124-nyan-blaze-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/tegra124-car.h> 7 emc-timings-1 { 8 nvidia,ram-code = <1>; 10 timing-12750000 { 11 clock-frequency = <12750000>; 12 nvidia,parent-clock-frequency = <408000000>; 14 clock-names = "emc-parent"; 17 timing-20400000 { 18 clock-frequency = <20400000>; [all …]
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H A D | tegra30-lg-p880.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra30-lg-x3.dtsi" 16 pinctrl-names = "default"; 17 pinctrl-0 = <&state_default>; 21 host-wlan-wake { 26 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 29 /* GNSS UART-B pinmux */ 30 uartb-rxd { 35 nvidia,enable-input = <TEGRA_PIN_ENABLE>; [all …]
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H A D | tegra30-lg-p895.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra30-lg-x3.dtsi" 11 pinctrl-names = "default"; 12 pinctrl-0 = <&state_default>; 15 /* GNSS UART-B pinmux */ 16 uartb-cts-rxd { 22 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 24 uartb-rts-txd { 30 nvidia,enable-input = <TEGRA_PIN_DISABLE>; [all …]
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H A D | tegra30-pegatron-chagall.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/gpio-keys.h> 5 #include <dt-bindings/input/input.h> 6 #include <dt-bindings/thermal/thermal.h> 9 #include "tegra30-cpu-opp.dtsi" 10 #include "tegra30-cpu-opp-microvolt.dtsi" 11 #include "tegra30-asus-lvds-display.dtsi" 16 chassis-type = "tablet"; 35 * pre-existing /chosen node to be available to insert the [all …]
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H A D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 memory-controller@7000f000 { 5 emc-timings-0 { 6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ 8 timing-25500000 { 9 clock-frequency = <25500000>; 11 nvidia,emem-configuration = < 33 timing-51000000 { 34 clock-frequency = <51000000>; 36 nvidia,emem-configuration = < [all …]
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H A D | tegra124-nyan-big-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/tegra124-car.h> 7 emc-timings-1 { 8 nvidia,ram-code = <1>; 10 timing-12750000 { 11 clock-frequency = <12750000>; 12 nvidia,parent-clock-frequency = <408000000>; 14 clock-names = "emc-parent"; 17 timing-20400000 { 18 clock-frequency = <20400000>; [all …]
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H A D | tegra30-asus-nexus7-tilapia-memory-timings.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi" 12 memory-controller@7000f400 { 13 emc-timings-0 { 14 timing-667000000 { 15 clock-frequency = <667000000>; 17 nvidia,emc-auto-cal-interval = <0x001fffff>; 18 nvidia,emc-mode-1 = <0x80100002>; 19 nvidia,emc-mode-2 = <0x80200018>; 20 nvidia,emc-mode-reset = <0x80000b71>; [all …]
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H A D | tegra30-ouya.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/gpio-keys.h> 5 #include <dt-bindings/input/input.h> 6 #include <dt-bindings/thermal/thermal.h> 9 #include "tegra30-cpu-opp.dtsi" 10 #include "tegra30-cpu-opp-microvolt.dtsi" 26 stdout-path = "serial0:115200n8"; 30 trusted-foundations { 31 compatible = "tlm,trusted-foundations"; [all …]
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/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | nvidia,tegra30-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dmitry Osipenko <digetx@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Thierry Reding <thierry.reding@gmail.com> 15 The EMC interfaces with the off-chip SDRAM to service the request stream 16 sent from Memory Controller. The EMC also has various performance-affecting 17 settings beyond the obvious SDRAM configuration parameters and initialization [all …]
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H A D | nvidia,tegra124-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The EMC interfaces with the off-chip SDRAM to service the request stream 19 const: nvidia,tegra124-emc 26 - description: external memory clock 28 clock-names: [all …]
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H A D | nvidia,tegra20-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dmitry Osipenko <digetx@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Thierry Reding <thierry.reding@gmail.com> 15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to 16 service the request stream sent from Memory Controller. The EMC also has 17 various performance-affecting settings beyond the obvious SDRAM configuration [all …]
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H A D | nvidia,tegra30-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dmitry Osipenko <digetx@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Thierry Reding <thierry.reding@gmail.com> 30 Global Resources, which include things like configuration registers which 39 const: nvidia,tegra30-mc 47 clock-names: [all …]
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H A D | nvidia,tegra124-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Jon Hunter <jonathanh@nvidia.com> 11 - Thierry Reding <thierry.reding@gmail.com> 14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller. 22 const: nvidia,tegra124-mc 30 clock-names: 32 - const: mc [all …]
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/linux/Documentation/devicetree/bindings/firmware/ |
H A D | nvidia,tegra186-bpmp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 25 - .../mailbox/mailbox.txt 26 - .../mailbox/nvidia,tegra186-hsp.yaml 32 - .../clock/clock-bindings.txt 33 - <dt-bindings/clock/tegra186-clock.h> [all …]
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/linux/drivers/clk/tegra/ |
H A D | clk-tegra210-emc.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. 8 #include <linux/clk-provider.h> 53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local 57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent() 66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local 71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate() 72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate() 74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate() 75 * the parent and/or parent rate have changed as part of the EMC rate in tegra210_clk_emc_recalc_rate() [all …]
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/linux/Documentation/ABI/testing/ |
H A D | sysfs-firmware-efi | 24 Contact: linux-efi@vger.kernel.org 25 Description: Displays the physical addresses of all EFI Configuration 34 Contact: Narendra K <Narendra.K@dell.com>, linux-bugs@dell.com 35 Description: Displays the content of the Runtime Configuration Interface 36 Table version 2 on Dell EMC PowerEdge systems in binary format 37 Users: It is used by Dell EMC OpenManage Server Administrator tool to
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/linux/drivers/memory/tegra/ |
H A D | tegra30-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Based on downstream driver from NVIDIA and tegra124-emc.c 6 * Copyright (C) 2011-2014 NVIDIA Corporation 9 * Copyright (C) 2019 GRATE-DRIVER project 18 #include <linux/interconnect-provider.h> 387 * There are multiple sources in the EMC driver which could request 392 /* protect shared rate-change code path */ 398 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument 403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing() 405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing() [all …]
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/linux/drivers/scsi/device_handler/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # SCSI Device Handler configuration 30 tristate "EMC CLARiiON Device Handler" 33 If you have a EMC CLARiiON select y. Otherwise, say N. 36 tristate "SPC-3 ALUA Device Handler" 39 SCSI Device handler for generic SPC-3 Asymmetric Logical Unit
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/linux/arch/arm64/boot/dts/nvidia/ |
H A D | tegra194.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra194-clock.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h> 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 8 #include <dt-bindings/power/tegra194-powergate.h> 9 #include <dt-bindings/reset/tegra194-reset.h> 10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h> [all …]
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