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Searched +full:emc +full:- +full:cfg +full:- +full:periodic +full:- +full:qrst (Results 1 – 11 of 11) sorted by relevance

/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-asus-tf201.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
19 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 /* Azurewave AW-NH615 BCM4329B1 */
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H A Dtegra30-asus-tf300t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300t-init-hog {
13 gpio-hog;
15 output-low;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra30-asus-tf300tg.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300tg-init-hog {
13 gpio-hog;
28 output-low;
39 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
47 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
55 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-inpu
[all...]
H A Dtegra30-lg-p880.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
16 pinctrl-names = "default";
17 pinctrl-0 = <&state_default>;
21 host-wlan-wake {
26 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
29 /* GNSS UART-B pinmux */
30 uartb-rxd {
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra30-lg-p895.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
11 pinctrl-names = "default";
12 pinctrl-0 = <&state_default>;
15 /* GNSS UART-B pinmux */
16 uartb-cts-rxd {
22 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
24 uartb-rts-txd {
30 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
H A Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-op
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H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 memory-controller@7000f000 {
5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
8 timing-25500000 {
9 clock-frequency = <25500000>;
11 nvidia,emem-configuration = <
33 timing-51000000 {
34 clock-frequency = <51000000>;
36 nvidia,emem-configuration = <
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H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
12 memory-controller@7000f400 {
13 emc-timings-0 {
14 timing-667000000 {
15 clock-frequency = <667000000>;
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
[all …]
H A Dtegra30-ouya.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-op
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
[all …]