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Searched +full:emac +full:- +full:splitter (Results 1 – 3 of 3) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsocfpga-dwmac.txt9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
18 bit for each emac to enable/disable signals from the FPGA fabric to the
19 EMAC modules.
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
25 DWMAC controller is connected emac splitter.
26 phy-mode: The phy mode the ethernet operates in
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H A Daltr,socfpga-stmmac.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthew Gerlach <matthew.gerlach@altera.com>
16 # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
24 - altr,socfpga-stmmac
25 - altr,socfpga-stmmac-a10-s10
26 - altr,socfpga-stmmac-agilex5
29 - compatible
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H A Daltr,gmii-to-sgmii-2.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/net/altr,gmii-to-sgmii-2.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Matthew Gerlach <matthew.gerlach@altera.com>
18 const: altr,gmii-to-sgmii-2.0
22 - description: Registers for the emac splitter IP
23 - description: Registers for the GMII to SGMII converter.
24 - description: Registers for TSE control.
26 reg-names:
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