/freebsd/sys/contrib/device-tree/Bindings/dma/ |
H A D | fsl-edma.txt | 1 * Freescale enhanced Direct Memory Access(eDMA) Controller 3 The eDMA channels have multiplex capability by programmble memory-mapped 8 * eDMA Controller 10 - compatible : 11 - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC 12 - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp 13 - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the 15 - reg : Specifies base physical address(s) and size of the eDMA registers. 16 The 1st region is eDMA control register's address and size. 19 - interrupts : A list of interrupt-specifiers, one for each entry in [all …]
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H A D | fsl,edma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Freescale enhanced Direct Memory Access(eDMA) Controller 10 The eDMA channels have multiplex capability by programmable 11 memory-mapped registers. channels are split into two groups, called 16 - Peng Fan <peng.fan@nxp.com> 21 - enum: 22 - fsl,vf610-edma [all …]
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/freebsd/sys/arm/freescale/vybrid/ |
H A D | vf_sai.c | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 120 * MCLK - master clock 121 * nch - number of channels 122 * LRCLK - left right clock 183 { -1, 0 } 202 sc = scp->sc; in saimixer_init() 205 return -1; in saimixer_init() 209 snd_mtxlock(sc->lock); in saimixer_init() 210 pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL); in saimixer_init() [all …]
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H A D | vf_edma.c | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 30 * Vybrid Family Enhanced Direct Memory Access Controller (eDMA) 73 { -1, 0 } 83 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-edma")) in edma_probe() 86 device_set_desc(dev, "Vybrid Family eDMA Controller"); in edma_probe() 106 if (ch->enabled == 1) { in edma_transfer_complete_intr() 107 if (ch->ih != NULL) { in edma_transfer_complete_intr() 108 ch->ih(ch->ih_user, i); in edma_transfer_complete_intr() 128 device_printf(sc->dev, "DMA_ERR 0x%08x, ES 0x%08x\n", in edma_err_intr() [all …]
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/freebsd/sys/contrib/device-tree/Bindings/pci/ |
H A D | rockchip-dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shawn Lin <shawn.lin@rock-chips.com> 11 - Simon Xue <xxm@rock-chips.com> 12 - Heiko Stuebner <heiko@sntech.de> 22 - description: AHB clock for PCIe master 23 - description: AHB clock for PCIe slave 24 - description: AHB clock for PCIe dbi [all …]
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H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Jingoo Han <jingoohan1@gmail.com> 11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller 17 # and make sure it's assigned with the vendor-specific compatible string. 21 const: snps,dw-pcie-ep 23 - compatible [all …]
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H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Jingoo Han <jingoohan1@gmail.com> 11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 16 # Please create a separate DT-schema for your DWC PCIe Root Port controller 17 # and make sure it's assigned with the vendor-specific compatible string. 21 const: snps,dw-pcie 23 - compatible [all …]
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/freebsd/sys/arm/ti/ |
H A D | ti_edma3.c | 1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 101 * We use one-element array in case if we need to add 113 { -1, 0, 0 } 119 { -1, 0, 0 } 123 #define ti_edma3_cc_rd_4(reg) bus_read_4(ti_edma3_sc->mem_res[0], reg) 124 #define ti_edma3_cc_wr_4(reg, val) bus_write_4(ti_edma3_sc->mem_res[0], reg, val) 134 { ti_edma3_intr_comp, "EDMA Completion Interrupt" }, 135 { ti_edma3_intr_mperr, "EDMA Memory Protection Error Interrupt" }, [all …]
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/freebsd/sys/dev/mvs/ |
H A D | mvs.h | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 42 #define IC_HC0 0x000001ff /* bits 0-8 = HC0 */ 44 #define IC_HC1 (IC_HC0 << IC_HC_SHIFT) /* 9-17 = HC1 */ 58 #define IC_MAIN_RSVD (0xfe000000) /* bits 31-25 */ 59 #define IC_MAIN_RSVD_5 (0xfff10000) /* bits 31-19 */ 60 #define IC_MAIN_RSVD_SOC (0xfffffec0) /* bits 31-9, 7-6 */ 65 #define CHIP_SOC_HC0_MASK(num) (0xff >> ((4 - (num)) * 2)) 87 #define HC_RQOP 0x4 /* Request Queue Out-Pointer */ 88 #define HC_RQIP 0x8 /* Response Queue In-Pointer */ [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/ |
H A D | vfxxx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 5 #include "vf610-pinfunc.h" 6 #include <dt-bindings/clock/vf610-clock.h> 7 #include <dt-bindings/interrupt-controller/irq.h> 8 #include <dt-bindings/gpio/gpio.h> 32 compatible = "fixed-cloc [all...] |
/freebsd/sys/contrib/device-tree/Bindings/iommu/ |
H A D | ti,omap-iommu.txt | 4 - compatible : Should be one of, 5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances 6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances 7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances 8 "ti,dra7-iommu" for DRA7xx IOMMU instances 9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance 10 - reg : Address space for the configuration registers 11 - interrupts : Interrupt specifier for the IOMMU instance 12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices, 19 - ti,#tlb-entries : Number of entries in the translation look-aside buffer. [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | fsl-ls1012a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1012A family SoC. 6 * Copyright 2019-2020 NXP 10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 23 rtic-a = &rtic_a; [all …]
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H A D | fsl-ls1043a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1043A family SoC. 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/gpio/gpio.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; [all …]
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H A D | fsl-ls1046a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/gpio/gpio.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 37 #address-cells = <1>; [all …]
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H A D | fsl-ls1028a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 5 * Copyright 2018-2020 NXP 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 22 #address-cells = <1>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nxp/ls/ |
H A D | ls1021a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/thermal/thermal.h> 10 #address-cells = <2>; 11 #size-cells = <2>; 12 interrupt-parent = <&gic>; 30 #address-cells = <1>; 31 #size-cells = <0>; 34 compatible = "arm,cortex-a7"; [all …]
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/freebsd/sys/dev/ath/ath_hal/ |
H A D | ah.h | 1 /*- 2 * SPDX-License-Identifier: ISC 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 26 * structure for use with the device. Hardware-related operations that 67 * error occurs--i.e. you cannot check it for success. 81 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 84 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 106 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 112 HAL_CAP_TPC = 16, /* per-packet tx power control */ [all …]
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | dra7.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/bus/ti-sysc.h> 9 #include <dt-bindings/clock/dra7.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/pinctrl/dra.h> 12 #include <dt-bindings/clock/dra7.h> 17 #address-cells = <2>; 18 #size-cells = <2>; 21 interrupt-parent = <&crossbar_mpu>; [all …]
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