| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
24 sensitive.
[all …]
|
| H A D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
|
| H A D | open-pic.txt | 13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
42 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
|
| H A D | atmel,aic.txt | 4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
22 - reg: Should contain AIC registers location and length
[all …]
|
| H A D | nxp,lpc3220-mic.txt | 4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
[all …]
|
| H A D | atmel,aic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma balasubiramani <dharma.b@microchip.com>
14 The Advanced Interrupt Controller (AIC) is an 8-level priority, individually
16 hundred and twenty-eight interrupt sources.
21 - atmel,at91rm9200-aic
22 - atmel,sama5d2-aic
[all …]
|
| H A D | interrupts.txt | 5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
45 -----------
[all …]
|
| H A D | img,meta-intc.txt | 8 - compatible: Specifies the compatibility list for the interrupt controller.
9 The type shall be <string> and the value shall include "img,meta-intc".
11 - num-banks: Specifies the number of interrupt banks (each of which can
14 - interrupt-controller: The presence of this property identifies the node
17 - #interrupt-cells: Specifies the number of cells needed to encode an
20 - #address-cells: Specifies the number of cells needed to encode an
22 'interrupt-map' nodes do not have to specify a parent unit address.
26 - no-mask: The controller doesn't have any mask registers.
32 - <1st-cell>: The interrupt-number that identifies the interrupt source.
34 - <2nd-cell>: The Linux interrupt flags containing level-sense information,
[all …]
|
| H A D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-nmk.txt | 4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
[all …]
|
| H A D | nvidia,tegra20-gpio.txt | 4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
19 4 = active high level-sensitive.
[all …]
|
| H A D | gpio-zynq.txt | 2 -------------------------------------------
5 - #gpio-cells : Should be two
6 - First cell is the GPIO line number
7 - Second cell is used to specify optional
9 - compatible : Should be "xlnx,zynq-gpio-1.0" or
10 "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
11 or "xlnx,pmc-gpio-1.0
12 - clocks : Clock specifier (see clock bindings for details)
13 - gpio-controller : Marks the device node as a GPIO controller.
14 - interrupts : Interrupt specifier (see interrupt bindings for
[all …]
|
| H A D | gpio-omap.txt | 4 - compatible:
5 - "ti,omap2-gpio" for OMAP2 controllers
6 - "ti,omap3-gpio" for OMAP3 controllers
7 - "ti,omap4-gpio" for OMAP4 controllers
8 - reg : Physical base address of the controller and length of memory mapped
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two.
12 - first cell is the pin number
13 - second cell is used to specify optional parameters (unused)
14 - interrupt-controller: Mark the device node as an interrupt controller.
[all …]
|
| H A D | gpio-xlp.txt | 10 -------------------
12 - compatible: Should be one of the following:
13 - "netlogic,xlp832-gpio": For Netlogic XLP832
14 - "netlogic,xlp316-gpio": For Netlogic XLP316
15 - "netlogic,xlp208-gpio": For Netlogic XLP208
16 - "netlogic,xlp980-gpio": For Netlogic XLP980
17 - "netlogic,xlp532-gpio": For Netlogic XLP532
18 - "brcm,vulcan-gpio": For Broadcom Vulcan ARM64
19 - reg: Physical base address and length of the controller's registers.
20 - #gpio-cells: Should be two. The first cell is the pin number and the second
[all …]
|
| H A D | gpio-vf610.txt | 8 - compatible : Should be "fsl,<soc>-gpio", below is supported list:
9 "fsl,vf610-gpio"
10 "fsl,imx7ulp-gpio"
11 - reg : The first reg tuple represents the PORT module, the second tuple
13 - interrupts : Should be the port interrupt shared by all 32 pins.
14 - gpio-controller : Marks the device node as a gpio controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and
19 - interrupt-controller: Marks the device node as an interrupt controller.
20 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
22 1 = low-to-high edge triggered.
[all …]
|
| H A D | nvidia,tegra20-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
[all …]
|
| H A D | brcm,brcmstb-gpio.txt | 3 The controller's registers are organized as sets of eight 32-bit
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
30 - interrupts:
33 - interrupts-extended:
[all …]
|
| H A D | socionext,uniphier-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
[all …]
|
| H A D | brcm,brcmstb-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The controller's registers are organized as sets of eight 32-bit
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
23 - const: brcm,brcmstb-gpio
[all …]
|
| H A D | gpio-mvebu.txt | 5 - compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
6 "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
8 "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
9 Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
12 "marvel,armadaxp-gpio" should be used for all Armada XP SoCs
15 "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
17 Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
20 - reg: Address and length of the register set for the device. Only one
21 entry is expected, except for the "marvell,armadaxp-gpio" variant
23 one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
[all …]
|
| H A D | nvidia,tegra186-gpio.txt | 42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
52 both the overall controller HW module and the sets-of-ports as "controllers".
56 interrupt signals generated by a set-of-ports. The intent is for each generated
59 per-port-set signals is reported via a separate register. Thus, a driver needs
66 - compatible
69 - "nvidia,tegra186-gpio".
70 - "nvidia,tegra186-gpio-aon".
71 - "nvidia,tegra194-gpio".
72 - "nvidia,tegra194-gpio-aon".
[all …]
|
| H A D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
53 controller, are both extremely non-linear. The header file
54 <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
65 module and the sets-of-ports as "controllers".
69 one of the interrupt signals generated by a set-of-ports. The intent is
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | qcom-pm8xxx.txt | 1 Qualcomm PM8xxx PMIC multi-function devices
8 - compatible:
16 - #address-cells:
21 - #size-cells:
26 - interrupts:
28 Value type: <prop-encoded-array>
34 - #interrupt-cells:
42 1 = low-to-high edge triggered
43 2 = high-to-low edge triggered
44 4 = active high level-sensitive
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | brcm,bcm2835-gpio.txt | 7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | mpic.txt | 14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
47 - pic-no-reset
53 configuration registers to a sane state-- masked or
60 - big-endian
[all …]
|