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/linux/Documentation/devicetree/bindings/mtd/
H A Dnand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
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H A Dmxicy,nand-ecc-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Macronix NAND ECC engine
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 const: mxicy,nand-ecc-engine-rev3
26 - compatible
27 - reg
32 - |
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H A Dmediatek,nand-ecc-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek(MTK) SoCs NAND ECC engine
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
18 - mediatek,mt2701-ecc
19 - mediatek,mt2712-ecc
20 - mediatek,mt7622-ecc
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H A Dmediatek,mtk-nfc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
15 - mediatek,mt2701-nfc
16 - mediatek,mt2712-nfc
17 - mediatek,mt7622-nfc
21 - description: Base physical address and size of NFI.
25 - description: NFI interrupt
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H A Draw-nand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
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H A Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
6 The NAND controller might be connected to an ECC engine.
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
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H A Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
14 - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
25 - description: Bank number, offset and size of first attached NAND chip
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H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
18 is paired with a custom DMA engine (inventively named "Flash DMA") which
27 -- Additional SoC-specific NAND controller properties --
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/linux/drivers/mtd/nand/raw/ingenic/
H A Dingenic_ecc.c1 // SPDX-License-Identifier: GPL-2.0
3 * JZ47xx ECC common code
19 * ingenic_ecc_calculate() - calculate ECC for a data buffer
20 * @ecc: ECC device.
21 * @params: ECC parameters.
23 * @ecc_code: output buffer with ECC.
25 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
28 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
32 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
36 * ingenic_ecc_correct() - detect and correct bit errors
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/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-mtk-snfi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
17 in single, dual or quad IO mode with pipelined ECC encoding/decoding
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H A Dqcom,spi-qpic-snand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md sadre Alam <quic_mdalam@quicinc.com>
13 The QCOM QPIC-SPI-NAND flash controller is an extended version of
15 and parallel mode. It supports typical SPI-NAND page cache
16 operations in single, dual or quad IO mode with pipelined ECC
17 encoding/decoding using the QPIC ECC HW engine.
20 - $ref: /schemas/spi/spi-controller.yaml#
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H A Dmxicy,mx25f0a-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mxicy,mx25f0a-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: spi-controller.yaml#
17 const: mxicy,mx25f0a-spi
23 reg-names:
25 - const: regs
26 - const: dirmap
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/linux/include/linux/
H A Dccp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 * ccp_present - check if a CCP device is present
29 * Returns zero if a CCP device is present, -ENODEV otherwise.
34 #define CCP_VMASK ((unsigned int)((1 << CCP_VSIZE) - 1))
39 * ccp_version - get the version of the CCP
46 * ccp_enqueue_cmd - queue an operation for processing by the CCP
55 * result in a return code of -EBUSY.
61 * will be -EINPROGRESS. Any other "err" value during callback is
65 * the return code is -EINPROGRESS or
66 * the return code is -EBUSY and CCP_CMD_MAY_BACKLOG flag is set
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/linux/drivers/mtd/nand/raw/
H A Dnuvoton-ma35d1-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/dma-mapping.h>
73 /* Define for the BCH hardware ECC engine */
119 return -ERANGE; in ma35_ooblayout_ecc()
121 oob_region->length = chip->ecc.total; in ma35_ooblayout_ecc()
122 oob_region->offset = mtd->oobsize - oob_region->length; in ma35_ooblayout_ecc()
133 return -ERANGE; in ma35_ooblayout_free()
135 oob_region->length = mtd->oobsize - chip->ecc.total - 2; in ma35_ooblayout_free()
136 oob_region->offset = 2; in ma35_ooblayout_free()
143 .ecc = ma35_ooblayout_ecc,
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H A Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
150 * struct anand - Defines the NAND chip related information
153 * @rb: Ready-busy line
157 * @timings: NV-DDR specific timings to use
158 * @ecc_conf: Hardware ECC configuration value
159 * @strength: Register value of the ECC strength
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H A Dcadence-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
26 * - PIO - can work in master or slave DMA
27 * - CDMA - needs Master DMA for accessing command descriptors.
28 * - Generic mode - can use only slave DMA.
90 /* Command Engine threads state. */
93 /* Command Engine interrupt thread error status. */
95 /* Command Engine interrupt thread error enable. */
97 /* Command Engine interrupt thread complete status. */
117 /* Size of not-last data sector. */
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H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
23 * bytes (also called "spare" bytes in the driver). This engine
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30 * +-------------------------------------------------------------+
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H A Dplat_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
24 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in plat_nand_attach_chip()
25 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in plat_nand_attach_chip()
26 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in plat_nand_attach_chip()
40 struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev); in plat_nand_probe()
47 dev_err(&pdev->dev, "platform_nand_data is missing\n"); in plat_nand_probe()
48 return -EINVAL; in plat_nand_probe()
51 if (pdata->chip.nr_chips < 1) { in plat_nand_probe()
52 dev_err(&pdev->dev, "invalid number of chips specified\n"); in plat_nand_probe()
53 return -EINVAL; in plat_nand_probe()
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H A Dtechnologic-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
47 switch (chip->ecc.engine_type) { in ts72xx_nand_attach_chip()
49 return -EINVAL; in ts72xx_nand_attach_chip()
51 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in ts72xx_nand_attach_chip()
52 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in ts72xx_nand_attach_chip()
53 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in ts72xx_nand_attach_chip()
63 unsigned char bits = ioread8(data->ctrl) & ~GENMASK(2, 0); in ts72xx_nand_ctrl()
65 iowrite8(bits | value, data->ctrl); in ts72xx_nand_ctrl()
76 switch (instr->type) { in ts72xx_nand_exec_instr()
79 iowrite8(instr->ctx.cmd.opcode, data->base); in ts72xx_nand_exec_instr()
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/linux/include/linux/mtd/
H A Dnand-ecc-sw-bch.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This file is the header for the NAND BCH ECC implementation.
15 * struct nand_ecc_sw_bch_conf - private software BCH ECC engine structure
17 * engine needs
19 * @calc_buf: Buffer to use when calculating ECC bytes
20 * @code_buf: Buffer to use when reading (raw) ECC bytes from the chip
23 * @eccmask: XOR ecc mask, allows erased pages to be decoded as valid
51 return -ENOTSUPP; in nand_ecc_sw_bch_calculate()
59 return -ENOTSUPP; in nand_ecc_sw_bch_correct()
64 return -ENOTSUPP; in nand_ecc_sw_bch_init_ctx()
H A Dnand-ecc-sw-hamming.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2000-2010 Steven J. Hill <sjhill@realitydiluted.com>
7 * This file is the header for the NAND Hamming ECC implementation.
16 * struct nand_ecc_sw_hamming_conf - private software Hamming ECC engine structure
18 * engine needs
20 * @calc_buf: Buffer to use when calculating ECC bytes
21 * @code_buf: Buffer to use when reading (raw) ECC bytes from the chip
52 return -ENOTSUPP; in nand_ecc_sw_hamming_init_ctx()
61 return -ENOTSUPP; in ecc_sw_hamming_calculate()
68 return -ENOTSUPP; in nand_ecc_sw_hamming_calculate()
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/linux/drivers/mtd/nand/
H A Decc-sw-bch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file provides ECC correction for more than 1 bit per block of data,
15 #include <linux/mtd/nand-ecc-sw-bch.h>
18 * nand_ecc_sw_bch_calculate - Calculate the ECC corresponding to a data block
21 * @code: Output buffer with ECC
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
29 memset(code, 0, engine_conf->code_size); in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
33 for (i = 0; i < engine_conf->code_size; i++) in nand_ecc_sw_bch_calculate()
34 code[i] ^= engine_conf->eccmask[i]; in nand_ecc_sw_bch_calculate()
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H A Decc-mtk.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * MTK ECC controller driver.
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-mtk.h>
71 /* ecc strength that each IP supports */
126 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, in mtk_ecc_wait_idle() argument
129 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
143 struct mtk_ecc *ecc = id; in mtk_ecc_irq() local
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/linux/drivers/crypto/aspeed/
H A DKconfig2 tristate "Support for Aspeed cryptographic engine driver"
6 Hash and Crypto Engine (HACE) is designed to accelerate the
22 bool "Enable Aspeed Hash & Crypto Engine (HACE) hash"
29 Select here to enable Aspeed Hash & Crypto Engine (HACE)
32 SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, and so on.
35 bool "Enable Aspeed Hash & Crypto Engine (HACE) crypto"
43 Select here to enable Aspeed Hash & Crypto Engine (HACE)
45 Supports AES/DES symmetric-key encryption and decryption
49 bool "Enable Aspeed ACRY RSA Engine"
54 Select here to enable Aspeed ECC/RSA Engine (ACRY)
/linux/Documentation/devicetree/bindings/crypto/
H A Daspeed,ast2600-acry.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neal Liu <neal_liu@aspeedtech.com>
15 divided into two independent engines - ECC Engine and RSA Engine.
20 - aspeed,ast2600-acry
24 - description: acry base address & size
25 - description: acry sram base address & size
34 - compatible
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