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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dnand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
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H A Dmxicy,nand-ecc-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Macronix NAND ECC engine
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 const: mxicy,nand-ecc-engine-rev3
26 - compatible
27 - reg
32 - |
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H A Dmtk-nand.txt5 the nand controller interface driver and the ECC engine driver.
15 - compatible: Should be one of
16 "mediatek,mt2701-nfc",
17 "mediatek,mt2712-nfc",
18 "mediatek,mt7622-nfc".
19 - reg: Base physical address and size of NFI.
20 - interrupts: Interrupts of NFI.
21 - clocks: NFI required clocks.
22 - clock-names: NFI clocks internal name.
23 - ecc-engine: Required ECC Engine node.
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H A Dmediatek,nand-ecc-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek(MTK) SoCs NAND ECC engine
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
18 - mediatek,mt2701-ecc
19 - mediatek,mt2712-ecc
20 - mediatek,mt7622-ecc
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H A Dmediatek,mtk-nfc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
15 - mediatek,mt2701-nfc
16 - mediatek,mt2712-nfc
17 - mediatek,mt7622-nfc
21 - description: Base physical address and size of NFI.
25 - description: NFI interrupt
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H A Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
6 The NAND controller might be connected to an ECC engine.
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
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H A Draw-nand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
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H A Dgpmc-nand.txt7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
10 For NAND specific properties such as ECC modes or bus width, please refer to
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
23 - nand-bus-width: Set this numeric value to 16 if the hardware
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
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H A Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
14 - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
25 - description: Bank number, offset and size of first attached NAND chip
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H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
18 is paired with a custom DMA engine (inventively named "Flash DMA") which
27 -- Additional SoC-specific NAND controller properties --
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H A Dbrcm,brcmnand.txt3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
6 paired with a custom DMA engine (inventively named "Flash DMA") which supports
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
25 brcm,brcmnand-v4.0
26 brcm,brcmnand-v5.0
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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dmediatek,spi-mtk-snfi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
17 in single, dual or quad IO mode with pipelined ECC encoding/decoding
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H A Dmxicy,mx25f0a-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mxicy,mx25f0a-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: spi-controller.yaml#
17 const: mxicy,mx25f0a-spi
23 reg-names:
25 - const: regs
26 - const: dirmap
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/freebsd/crypto/openssl/crypto/ec/
H A Dec_key.c2 * Copyright 2002-2022 The OpenSSL Project Authors. All Rights Reserved.
23 # include <openssl/engine.h>
50 ret->group = EC_GROUP_new_by_curve_name_ex(ctx, propq, nid); in EC_KEY_new_by_curve_name_ex()
51 if (ret->group == NULL) { in EC_KEY_new_by_curve_name_ex()
55 if (ret->meth->set_group != NULL in EC_KEY_new_by_curve_name_ex()
56 && ret->meth->set_group(ret, ret->group) == 0) { in EC_KEY_new_by_curve_name_ex()
77 CRYPTO_DOWN_REF(&r->references, &i, r->lock); in EC_KEY_free()
83 if (r->meth != NULL && r->meth->finish != NULL) in EC_KEY_free()
84 r->meth->finish(r); in EC_KEY_free()
87 ENGINE_finish(r->engine); in EC_KEY_free()
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/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Daspeed,ast2600-acry.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neal Liu <neal_liu@aspeedtech.com>
15 divided into two independent engines - ECC Engine and RSA Engine.
20 - aspeed,ast2600-acry
24 - description: acry base address & size
25 - description: acry sram base address & size
34 - compatible
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/freebsd/sys/contrib/device-tree/src/mips/ingenic/
H A Drs90.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/iio/adc/ingenic,adc.h>
8 #include <dt-bindings/input/linux-event-codes.h>
12 model = "RS-90";
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
24 vmem: video-memory@1f00000 {
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H A Dqi_lb60.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/iio/adc/ingenic,adc.h>
8 #include <dt-bindings/clock/ingenic,tcu.h>
9 #include <dt-bindings/input/input.h>
27 stdout-path = &uart0;
30 vcc: regulator-0 {
31 compatible = "regulator-fixed";
32 regulator-name = "vcc";
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H A Dci20.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/clock/ingenic,tcu.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/regulator/active-semi,8865-regulator.h>
22 stdout-path = &uart4;
31 gpio-keys {
32 compatible = "gpio-keys";
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/freebsd/sys/dev/qat/qat_api/common/include/
H A Dlac_sal_types_crypto.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
71 /**< pointer to an array of atomic stats for Ecc */
74 /**< pointer to an array of atomic stats for Ecc DH */
77 /**< pointer to an array of atomic stats for Ecc DSA */
91 /**< Flow ID for all pke requests from this instance - identifies
93 and execution engine to use */
130 /**< table of pointers to CD for Hmac precomputes - used at session init
/freebsd/sys/crypto/ccp/
H A Dccp_hardware.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
69 /* Don't think there's much point in keeping these -- OS can't access: */
249 * 8 32-bit words:
250 * word 0: function; engine; control bits
273 uint32_t engine:4; member
287 uint32_t engine:4; member
301 uint32_t engine:4; member
314 uint32_t engine:4; member
326 uint32_t engine:4; member
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/freebsd/secure/usr.bin/openssl/man/
H A Dopenssl-dgst.118 .\" Set up some character translations and predefined strings. \*(-- will
24 .tr \(*W-
27 . ds -- \(*W-
29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
37 . ds -- \|\(em\|
71 .\" Fear. Run. Save yourself. No user-serviceable parts.
81 . ds #H ((1u-(\\\\n(.fu%2u))*.13m)
97 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
98 . ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
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/freebsd/crypto/openssl/doc/man1/
H A Dopenssl-dgst.pod.in2 {- OpenSSL::safe::output_do_not_edit_headers(); -}
6 openssl-dgst - perform digest operations
11 [B<-I<digest>>]
12 [B<-list>]
13 [B<-help>]
14 [B<-c>]
15 [B<-d>]
16 [B<-debug>]
17 [B<-hex>]
18 [B<-binary>]
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/freebsd/contrib/unbound/sldns/
H A Dkeyraw.h2 * keyraw.h -- raw key and signature access and conversion
4 * Copyright (c) 2005-2008, NLnet Labs. All rights reserved.
57 /** Release the engine reference held for the GOST engine. */
92 * \param[in] algo precise algorithm to initialize ECC group values.
/freebsd/crypto/openssl/
H A DNEWS.md8 ----------------
10 - [OpenSSL 3.0](#openssl-30)
11 - [OpenSSL 1.1.1](#openssl-111)
12 - [OpenSSL 1.1.0](#openssl-110)
13 - [OpenSSL 1.0.2](#openssl-102)
14 - [OpenSSL 1.0.1](#openssl-101)
15 - [OpenSSL 1.0.0](#openssl-100)
16 - [OpenSSL 0.9.x](#openssl-09x)
19 -----------
28 * Fixed timing side-channel in ECDSA signature computation.
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/freebsd/contrib/ldns/
H A Dkeys.c8 * (c) NLnet Labs, 2004-2006
27 #include <openssl/engine.h>
34 { LDNS_SIGN_RSASHA1_NSEC3, "RSASHA1-NSEC3-SHA1" },
40 { LDNS_SIGN_ECC_GOST, "ECC-GOST" },
54 { LDNS_SIGN_DSA_NSEC3, "DSA-NSEC3-SHA1" },
56 { LDNS_SIGN_HMACMD5, "hmac-md5.sig-alg.reg.int" },
57 { LDNS_SIGN_HMACSHA1, "hmac-sha1" },
58 { LDNS_SIGN_HMACSHA256, "hmac-sha256" },
59 { LDNS_SIGN_HMACSHA224, "hmac-sha224" },
60 { LDNS_SIGN_HMACSHA384, "hmac-sha384" },
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