Searched +full:ec7tie1 +full:- +full:1 (Results 1 – 6 of 6) sorted by relevance
/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | renesas,rzg2l-irqc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 11 - Geert Uytterhoeven <geert+renesas@glider.be> 15 interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral 17 - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts 18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts 19 - NMI edge select (NMI is not treated as NMI exception and supports fall edge and [all …]
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/linux/arch/riscv/boot/dts/renesas/ |
H A D | r9a07g043f.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/interrupt-controller/irq.h> 16 #address-cells = <1>; 17 #size-cells = <0>; 18 timebase-frequency = <12000000>; 23 #cooling-cells = <2>; 27 riscv,isa-base = "rv64i"; 28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 31 mmu-type = "riscv,sv39"; 32 i-cache-size = <0x8000>; [all …]
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/linux/arch/arm64/boot/dts/renesas/ |
H A D | r9a07g043u.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 16 #address-cells = <1>; 17 #size-cells = <0>; 20 compatible = "arm,cortex-a55"; 23 #cooling-cells = <2>; 24 next-level-cache = <&L3_CA55>; 25 enable-method = "psci"; 27 operating-points-v2 = <&cluster0_opp>; 30 L3_CA55: cache-controller-0 { [all …]
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H A D | r9a08g045.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/r9a08g045-cpg.h> 10 #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h> 14 #address-cells = <2>; 15 #size-cells = <2>; 18 #address-cells = <1>; 19 #size-cells = <0>; 22 compatible = "arm,cortex-a55"; 25 #cooling-cells = <2>; [all …]
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H A D | r9a07g054.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/r9a07g054-cpg.h> 13 #address-cells = <2>; 14 #size-cells = <2>; 16 audio_clk1: audio1-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 20 clock-frequency = <0>; 23 audio_clk2: audio2-clk { [all …]
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H A D | r9a07g044.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/r9a07g044-cpg.h> 13 #address-cells = <2>; 14 #size-cells = <2>; 16 audio_clk1: audio1-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 20 clock-frequency = <0>; 23 audio_clk2: audio2-clk { [all …]
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