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/linux/drivers/pci/controller/dwc/
H A Dpcie-rcar-gen4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe controller driver for Renesas R-Car Gen4 Series SoCs
4 * Copyright (C) 2022-2023 Renesas Electronics Corporation
6 * The r8a779g0 (R-Car V4H) controller requires a specific firmware to be
7 * provided, to initialize the PHY. Otherwise, the PCIe controller will not
24 #include "pcie-designware.h"
26 /* Renesas-specific */
27 /* PCIe Mode Setting Register 0 */
34 /* PCIe Interrupt Status 0 */
37 /* PCIe Interrupt Status 0 Enable */
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H A Dpcie-designware-plat.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe RC driver for Synopsys DesignWare Core
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
21 #include "pcie-designware.h"
57 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in dw_plat_pcie_ep_raise_irq()
83 struct dw_pcie *pci = dw_plat_pcie->pci; in dw_plat_add_pcie_port()
84 struct dw_pcie_rp *pp = &pci->pp; in dw_plat_add_pcie_port()
85 struct device *dev = &pdev->dev; in dw_plat_add_pcie_port()
88 pp->irq = platform_get_irq(pdev, 1); in dw_plat_add_pcie_port()
89 if (pp->irq < 0) in dw_plat_add_pcie_port()
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/linux/Documentation/ABI/testing/
H A Dsysfs-driver-xdata1 What: /sys/class/misc/drivers/dw-xdata-pcie.<device>/write
5 Description: Allows the user to enable the PCIe traffic generator which
6 will create write TLPs frames - from the Root Complex to the
7 Endpoint direction or to disable the PCIe traffic generator
13 echo 1 > /sys/class/misc/dw-xdata-pcie.<device>/write
15 echo 0 > /sys/class/misc/dw-xdata-pcie.<device>/write
17 The user can read the current PCIe link throughput generated
21 cat /sys/class/misc/dw-xdata-pcie.<device>/write
26 What: /sys/class/misc/dw-xdata-pcie.<device>/read
30 Description: Allows the user to enable the PCIe traffic generator which
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/linux/Documentation/misc-devices/
H A Ddw-xdata-pcie.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Driver for Synopsys DesignWare PCIe traffic generator (also known as xData)
8 Synopsys DesignWare PCIe prototype solution
17 -----------
19 This driver should be used as a host-side (Root Complex) driver and Synopsys
22 The dw-xdata-pcie driver can be used to enable/disable PCIe traffic
24 PCIe link performance analysis.
31 -------
33 Write TLPs traffic generation - Root Complex to Endpoint direction
38 # echo 1 > /sys/class/misc/dw-xdata-pcie.0/write
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/linux/Documentation/devicetree/bindings/pci/
H A Daxis,artpec6-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Axis ARTPEC-6 PCIe host controller
11 - Jesper Nilsson <jesper.nilsson@axis.com>
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
21 - axis,artpec6-pcie
22 - axis,artpec6-pcie-ep
23 - axis,artpec7-pcie
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H A Drockchip-dw-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
10 - Niklas Cassel <cassel@kernel.org>
13 RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
14 PCIe IP and thus inherits all the common properties defined in
15 snps,dw-pcie-ep.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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H A Drockchip-dw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
16 PCIe IP and thus inherits all the common properties defined in
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H A Dmarvell,armada8k-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada 7K/8K PCIe interface
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
13 This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
20 - marvell,armada8k-pcie
22 - compatible
25 - $ref: snps,dw-pcie.yaml#
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H A Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCIe RC controller on Intel Gateway SoCs
10 - Rahul Tanwar <rtanwar@maxlinear.com>
16 const: intel,lgm-pcie
18 - compatible
21 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - const: intel,lgm-pcie
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H A Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe endpoint interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller endpoint
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
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H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
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H A Dst,spear1340-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/st,spear1340-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST SPEAr1340 PCIe controller
10 - Pratyush Anand <pratyush.anand@gmail.com>
13 SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
20 const: st,spear1340-pcie
22 - compatible
27 - const: st,spear1340-pcie
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H A Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
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H A Dsamsung,exynos-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series PCIe Host Controller
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Jaehoon Chung <jh80.chung@samsung.com>
14 Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
15 PCIe IP and thus inherits all the common properties defined in
16 snps,dw-pcie.yaml.
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H A Dsophgo,sg2044-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/sophgo,sg2044-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Root Complex controller on Sophgo SoCs
10 - Inochi Amaoto <inochiama@gmail.com>
13 SG2044 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
14 PCIe IP and thus inherits all the common properties defined in
15 snps,dw-pcie.yaml.
18 - $ref: /schemas/pci/pci-host-bridge.yaml#
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H A Dsifive,fu740-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive FU740 PCIe host controller
10 SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Paul Walmsley <paul.walmsley@sifive.com>
17 - Greentime Hu <greentime.hu@sifive.com>
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H A Dti-pci.txt3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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H A Dhisilicon,kirin-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin SoCs PCIe host DT description
10 - Xiaowei Song <songxiaowei@hisilicon.com>
11 - Binghui Wang <wangbinghui@hisilicon.com>
14 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
15 It shares common functions with the PCIe DesignWare core driver and
17 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
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/linux/drivers/pci/pcie/
H A Dtlp.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe TLP Log handling
17 * aer_tlp_log_len - Calculate AER Capability TLP Header/Prefix Log length
18 * @dev: PCIe device
30 dev->eetlp_prefix_max : 0); in aer_tlp_log_len()
35 * dpc_tlp_log_len - Calculate DPC RP PIO TLP Header/Prefix Log length
36 * @dev: PCIe device
43 if (dev->dpc_rp_log_size >= PCIE_STD_NUM_TLP_HEADERLOG + 1) in dpc_tlp_log_len()
44 return dev->dpc_rp_log_size - 1; in dpc_tlp_log_len()
46 return dev->dpc_rp_log_size; in dpc_tlp_log_len()
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/linux/drivers/pci/controller/
H A Dpcie-altera.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
59 #define TLP_CFG_DW0(pcie, cfg) \ argument
62 #define TLP_CFG_DW1(pcie, tag, be) \ argument
63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
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/linux/drivers/dma/dw-edma/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_DW_EDMA) += dw-edma.o
4 dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o \
5 dw-hdma-v0-debugfs.o
6 dw-edma-objs := dw-edma-core.o \
7 dw-edma-v0-core.o \
8 dw-hdma-v0-core.o $(dw-edma-y)
9 obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o
H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
22 #include "dw-hdma-v0-core.h"
24 #include "../virt-dma.h"
35 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
37 if (chip->ops->pci_address) in dw_edma_get_pci_address()
38 return chip->ops->pci_address(chip->dev, cpu_addr); in dw_edma_get_pci_address()
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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
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/linux/include/linux/dma/
H A Dedma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
30 * struct dw_edma_core_ops - platform-specific eDMA methods
32 * method accepts the channel id in the end-to-end
35 * @pci_address: Get PCIe bus address corresponding to the passed CPU
38 * the DW PCIe RP/EP controller with the DW eDMA device in
56 * enum dw_edma_chip_flags - Flags specific to an eDMA chip
64 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
79 * @dw: struct dw_edma that is filled by dw_edma_probe()
101 struct dw_edma *dw; member
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/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
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