Searched full:dvc (Results 1 – 25 of 58) sorted by relevance
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3 // Renesas R-Car DVC support10 * amixer set "DVC Out" 100%13 * amixer set "DVC In" 100%16 * amixer set "DVC Out Mute" on19 * amixer set "DVC In Mute" on22 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"23 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"24 * amixer set "DVC Out Ramp" on26 * amixer set "DVC Out" 80% // Volume Down27 * amixer set "DVC Out" 100% // Volume Up[all …]
27 struct rsnd_mod *dvc = rsnd_io_to_mod_dvc(io); in rsnd_cmd_init() local38 if (!mix && !dvc) in rsnd_cmd_init()160 /* same number as DVC */ in rsnd_cmd_probe()
324 struct rsnd_mod *dvc = rsnd_io_to_mod_dvc(io); in rsnd_dmapp_get_id() local340 } else if (mod == dvc) { in rsnd_dmapp_get_id()584 dev_err(dev, "DVC is selected without SRC\n"); in rsnd_gen2_dma_addr()656 struct rsnd_mod *dvc = rsnd_io_to_mod_dvc(io); in rsnd_dma_of_path() local697 * [S] -*-> SRC -> DVC -o-> [E] in rsnd_dma_of_path()698 * [S] -*-> SRC -> CTU -> MIX -> DVC -o-> [E] in rsnd_dma_of_path()724 } else if (dvc) { in rsnd_dma_of_path()725 mod[idx++] = dvc; in rsnd_dma_of_path()726 dvc = NULL; in rsnd_dma_of_path()
2 snd-soc-rcar-y := core.o gen.o dma.o adg.o ssi.o ssiu.o src.o ctu.o mix.o dvc.o cmd.o debugfs.o
38 /* SCU (MIX/CTU/DVC) */487 #define RSND_NODE_DVC "rcar_sound,dvc"678 void *dvc; member854 * R-Car DVC861 rsnd_parse_connect_common(rdai, "dvc", rsnd_dvc_mod_get, \
21 * - DVC : Digital Volume and Mute Function31 * - DVC : Digital Volume and Mute Function391 * The point is [DVC] needs *Hardware* L/R, [MEM] needs *Software* L/R in rsnd_get_dalign()399 * [MEM] -> [SRC] -> [DVC] -> [CMD] -> [SSIU] -> [SSI] -> codec in rsnd_get_dalign()403 * codec -> [SSI] -> [SSIU] -> [SRC] -> [DVC] -> [CMD] -> [MEM] in rsnd_get_dalign()1841 * 1) Avoid duplicate register for DVC with MIX case in rsnd_kctrl_new()1904 * call "remove" for SSI/SRC/DVC in rsnd_rdai_continuance_probe()
9 * You can use Synchronous Sampling Rate Convert (if no DVC)443 * Enable SRC output if you want to use sync convert together with DVC in rsnd_src_start()
15 - DVC : Digital Volume and Mute Function34 See datasheet to check SRC/CTU/MIX/DVC connect-limitation.155 * DVC (Digital Volume and Mute Function)158 DVC controls Playback/Capture volume.161 amixer set "DVC Out" 100%164 amixer set "DVC In" 100%167 amixer set "DVC Out Mute" on170 amixer set "DVC In Mute" on173 amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"174 amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"[all …]
13 * amixer set "DVC Out" 100%14 * amixer set "DVC In" 100%18 * amixer set "DVC Out Mute" on19 * amixer set "DVC In Mute" on23 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"24 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"25 * amixer set "DVC Out Ramp" on27 * amixer set "DVC Out" 80% // Volume Down28 * amixer set "DVC Out" 100% // Volume Up
18 * amixer set "DVC Out" 100%19 * amixer set "DVC In" 100%23 * amixer set "DVC Out Mute" on24 * amixer set "DVC In Mute" on28 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"29 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"30 * amixer set "DVC Out Ramp" on32 * amixer set "DVC Out" 80% // Volume Down33 * amixer set "DVC Out" 100% // Volume Up
20 * amixer set "DVC Out" 100%21 * amixer set "DVC In" 100%25 * amixer set "DVC Out Mute" on26 * amixer set "DVC In Mute" on30 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"31 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"32 * amixer set "DVC Out Ramp" on34 * amixer set "DVC Out" 80% // Volume Down35 * amixer set "DVC Out" 100% // Volume Up
1052 "dvc.0", "dvc.1",1068 rcar_sound,dvc {1069 dvc0: dvc-0 {1073 dvc1: dvc-1 {
21 - description: Tegra20 has specific I2C controller called as DVC I2C24 generic I2C controller. Driver of DVC I2C controller is only25 compatible with "nvidia,tegra20-i2c-dvc".26 const: nvidia,tegra20-i2c-dvc
1079 "dvc.0", "dvc.1",1099 rcar_sound,dvc {1100 dvc0: dvc-0 {1104 dvc1: dvc-1 {
10 2 value conditions for the hardware watchpoints (DVC)38 unit32_t sizeof_condition; /* size of the DVC register */84 DAC and DVC registers will be set in the same request.
243 u8 mfc, dvc; in intel_rng_hw_init() local261 dvc = readb(intel_rng_hw->mem + INTEL_FWH_DEVICE_CODE_ADDRESS); in intel_rng_hw_init()275 (dvc != INTEL_FWH_DEVICE_CODE_8M && in intel_rng_hw_init()276 dvc != INTEL_FWH_DEVICE_CODE_4M)) { in intel_rng_hw_init()
211 __u32 sizeof_condition; /* size of the DVC register */236 __u64 condition_value; /* contents of the DVC register */
22 /* LDO1 with DVC[0..3] */45 /* BUCK1 with DVC[0..3] */
218 /* Some LDOs and DCDCs are DVC controlled which requires enabling of in da9052_regulator_set_voltage_sel()244 /* The DVC controlled LDOs and DCDCs ramp with 6.25mV/µs after enabling in da9052_regulator_set_voltage_time_sel()
242 * @is_dvc: identifies the DVC I2C controller, has a different register layout315 * in order to talk to the I2C block inside the DVC block.496 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)1639 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },1656 of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) in tegra_i2c_parse_dt()
794 SDHI, DVC, enumerator847 INTC_VECT(DVC, 0x4e0),978 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC1072 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },