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/linux/drivers/pwm/
H A Dpwm-ntxec.c16 * - The period and duty cycle can't be changed together in one atomic action.
44 * The time base used in the EC is 8MHz, or 125ns. Period and duty cycle are
57 int period, int duty) in ntxec_pwm_set_raw_period_and_duty_cycle() argument
62 * Changes to the period and duty cycle take effect as soon as the in ntxec_pwm_set_raw_period_and_duty_cycle()
65 * duty cycle is fully written. If, in such a case, the old duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
68 * To minimize the time between the changes to period and duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
74 { NTXEC_REG_DUTY_HIGH, ntxec_reg8(duty >> 8) }, in ntxec_pwm_set_raw_period_and_duty_cycle()
76 { NTXEC_REG_DUTY_LOW, ntxec_reg8(duty) }, in ntxec_pwm_set_raw_period_and_duty_cycle()
86 unsigned int period, duty; in ntxec_pwm_apply() local
93 duty = min_t(u64, state->duty_cycle, period); in ntxec_pwm_apply()
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H A Dpwm-sunplus.c17 * - In .apply() PWM output need to write register FREQ and DUTY. When first write FREQ
18 * done and not yet write DUTY, it has short timing gap use new FREQ and old DUTY.
58 u32 dd_freq, duty, mode0, mode1; in sunplus_pwm_apply() local
101 /* cal and set pwm duty */ in sunplus_pwm_apply()
109 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX; in sunplus_pwm_apply()
115 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, in sunplus_pwm_apply()
117 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty; in sunplus_pwm_apply()
119 writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_apply()
130 u32 mode0, dd_freq, duty; in sunplus_pwm_get_state() local
138 duty = readl(priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_get_state()
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H A Dpwm-sprd.c75 u32 val, duty, prescale; in sprd_pwm_get_state() local
99 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. in sprd_pwm_get_state()
102 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate in sprd_pwm_get_state()
110 duty = val & SPRD_PWM_DUTY_MSK; in sprd_pwm_get_state()
111 tmp = (prescale + 1) * NSEC_PER_SEC * duty; in sprd_pwm_get_state()
126 u32 prescale, duty; in sprd_pwm_config() local
132 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. in sprd_pwm_config()
139 duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns; in sprd_pwm_config()
148 * Note: Writing DUTY triggers the hardware to actually apply the in sprd_pwm_config()
149 * values written to MOD and DUTY to the output, so must keep writing in sprd_pwm_config()
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H A Dpwm-sifive.c19 * To compensate, this driver always **inverts** the duty value when reading
25 * - When changing both duty cycle and period, we cannot prevent in
27 * settings (new period length and old duty cycle).
28 * - The hardware cannot generate a 0% duty cycle.
129 u32 duty, val, inactive; in pwm_sifive_get_state() local
133 * PWM hardware uses 'inactive' counts in pwmcmp, so invert to get actual duty. in pwm_sifive_get_state()
134 * Here, 'inactive' is the low time and we compute duty as max_count - inactive. in pwm_sifive_get_state()
136 duty = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - inactive; in pwm_sifive_get_state()
138 state->enabled = duty > 0; in pwm_sifive_get_state()
145 state->duty_cycle = DIV_ROUND_UP_ULL((u64)duty * ddata->real_period, in pwm_sifive_get_state()
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H A Dpwm-iqs620a.c9 * to the duty cycle or enable/disable state.
10 * - Changes to the duty cycle or enable/disable state take effect immediately
12 * - The device cannot generate a 0% duty cycle. For duty cycles below 1 / 256
84 * The duty cycle generated by the device is calculated as follows: in iqs620_pwm_apply()
89 * (inclusive). Therefore the lowest duty cycle the device can generate in iqs620_pwm_apply()
92 * For lower duty cycles (e.g. 0), the PWM output is simply disabled to in iqs620_pwm_apply()
122 * Since the device cannot generate a 0% duty cycle, requests to do so in iqs620_pwm_get_state()
H A Dpwm-dwc-core.c124 u64 duty, period; in dwc_pwm_get_state() local
140 duty = (ld + 1) * dwc->clk_ns; in dwc_pwm_get_state()
142 period += duty; in dwc_pwm_get_state()
144 duty = (ld + 1) * dwc->clk_ns; in dwc_pwm_get_state()
145 period = duty * 2; in dwc_pwm_get_state()
150 state->duty_cycle = duty; in dwc_pwm_get_state()
H A Dpwm-airoha.c68 /* Flash(Duty) producer handles 2 generators in one 32-bit register */
76 * only use up to 8 different combinations of duty cycle and period at a time.
106 /* Duty cycle is relative with 255 corresponding to 100% */
222 * Unlike duty cycle zero, which can be handled by in airoha_pwm_get_generator()
223 * disabling PWM, a generator is needed for full duty in airoha_pwm_get_generator()
232 * a bucket to recycle (closer to the requested period/duty) in airoha_pwm_get_generator()
245 * duty cycle that isn't bigger than the requested duty_cycle. in airoha_pwm_get_generator()
251 /* Skip bucket that goes over the requested duty */ in airoha_pwm_get_generator()
303 /* Configure duty cycle */ in airoha_pwm_apply_bucket_config()
326 * Search for a bucket that already satisfies duty and period in airoha_pwm_consume_generator()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A Dfanpwm.c44 u32 divs, duty; in nvkm_fanpwm_get() local
47 ret = therm->func->pwm_get(therm, fan->func.line, &divs, &duty); in nvkm_fanpwm_get()
49 divs = max(divs, duty); in nvkm_fanpwm_get()
51 duty = divs - duty; in nvkm_fanpwm_get()
52 return (duty * 100) / divs; in nvkm_fanpwm_get()
63 u32 divs, duty; in nvkm_fanpwm_set() local
74 duty = ((divs * percent) + 99) / 100; in nvkm_fanpwm_set()
76 duty = divs - duty; in nvkm_fanpwm_set()
78 ret = therm->func->pwm_set(therm, fan->func.line, divs, duty); in nvkm_fanpwm_set()
91 u32 divs, duty; in nvkm_fanpwm_create() local
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H A Dfan.c39 int duty; in nvkm_fan_update() local
52 /* check that we're not already at the target duty cycle */ in nvkm_fan_update()
53 duty = fan->get(therm); in nvkm_fan_update()
54 if (duty == target) { in nvkm_fan_update()
60 if (!immediate && duty >= 0) { in nvkm_fan_update()
65 if (duty < target) in nvkm_fan_update()
66 duty = min(duty + 3, target); in nvkm_fan_update()
67 else if (duty > target) in nvkm_fan_update()
68 duty = max(duty - 3, target); in nvkm_fan_update()
70 duty = target; in nvkm_fan_update()
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H A Dbase.c44 u16 duty, i; in nvkm_therm_update_trip() local
59 duty = cur_trip->fan_duty; in nvkm_therm_update_trip()
62 duty = 0; in nvkm_therm_update_trip()
66 return duty; in nvkm_therm_update_trip()
74 u16 duty; in nvkm_therm_compute_linear_duty() local
83 duty = (temp - linear_min_temp); in nvkm_therm_compute_linear_duty()
84 duty *= (therm->fan->bios.max_duty - therm->fan->bios.min_duty); in nvkm_therm_compute_linear_duty()
85 duty /= (linear_max_temp - linear_min_temp); in nvkm_therm_compute_linear_duty()
86 duty += therm->fan->bios.min_duty; in nvkm_therm_compute_linear_duty()
87 return duty; in nvkm_therm_compute_linear_duty()
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H A Dgf119.c68 gf119_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gf119_fan_pwm_get() argument
77 *duty = nvkm_rd32(device, 0x00e118 + (indx * 8)); in gf119_fan_pwm_get()
82 *duty = nvkm_rd32(device, 0x0200dc) & 0x1fff; in gf119_fan_pwm_get()
90 gf119_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gf119_fan_pwm_set() argument
98 nvkm_wr32(device, 0x00e118 + (indx * 8), duty | 0x80000000); in gf119_fan_pwm_set()
101 nvkm_wr32(device, 0x0200dc, duty | 0x40000000); in gf119_fan_pwm_set()
H A Dfantog.c46 int duty; in nvkm_fantog_update() local
53 duty = !nvkm_gpio_get(gpio, 0, DCB_GPIO_FAN, 0xff); in nvkm_fantog_update()
54 nvkm_gpio_set(gpio, 0, DCB_GPIO_FAN, 0xff, duty); in nvkm_fantog_update()
56 if (percent != (duty * 100)) { in nvkm_fantog_update()
58 if (!duty) in nvkm_fantog_update()
H A Dgm107.c34 gm107_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gm107_fan_pwm_get() argument
38 *duty = nvkm_rd32(device, 0x10eb24) & 0x1fff; in gm107_fan_pwm_get()
43 gm107_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gm107_fan_pwm_set() argument
47 nvkm_wr32(device, 0x10eb14, duty | 0x80000000); in gm107_fan_pwm_set()
/linux/Documentation/hwmon/
H A Ddme1737.rst166 attribute that needs to be set to the maximum attainable RPM (fan at 100% duty-
178 manual mode, the fan speed is set by writing the duty-cycle value to the
180 current duty-cycle as set by the fan controller in the chip. All PWM outputs
191 duty-cycles: full, low, and min. Full is internally hard-wired to 255 (100%)
198 pwm[1-3]_auto_point2_pwm full-speed duty-cycle (255, i.e., 100%)
199 pwm[1-3]_auto_point1_pwm low-speed duty-cycle
200 pwm[1-3]_auto_pwm_min min-speed duty-cycle
208 The chip adjusts the output duty-cycle linearly in the range of auto_point1_pwm
211 auto_point1_temp_hyst value, the output duty-cycle is set to the auto_pwm_min
214 duty-cycle. If any of the temperatures rise above the auto_point3_temp value,
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H A Dvt1211.rst181 Each PWM has 4 associated distinct output duty-cycles: full, high, low and
186 thermal thresholds exist that controls both PWMs output duty-cycles. The
194 PWM Auto Point PWM Output Duty-Cycle
196 pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255)
197 pwm[1-2]_auto_point3_pwm high speed duty-cycle
198 pwm[1-2]_auto_point2_pwm low speed duty-cycle
199 pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0)
212 PWM output duty-cycle based on the input temperature:
215 Thermal Threshold Output Duty-Cycle Output Duty-Cycle
218 - full speed duty-cycle full speed duty-cycle
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H A Dlm93.rst109 a minimum pulse width of 5 clocks (at 22.5kHz => 6.25% duty cycle), and
110 a maximum pulse width of 80 clocks (at 22.5kHz => 99.88% duty cycle).
115 contains a value controlling the duty cycle for the PWM signal used when
117 indicating minimum duty cycle and 15 indicating maximum.
148 and pwm2 are used to set the manual duty cycle; each is an integer (0-255)
149 where 0 is 0% duty cycle, and 255 is 100%. Note that the duty cycle values
152 PWM mode is disabled, the value of pwm1 and pwm2 indicates the current duty
238 A spin-up cycle occurs when a PWM output is commanded from 0% duty cycle to
239 some value > 0%. The LM93 supports a minimum duty cycle during spin-up. These
241 file has the same representation as other PWM duty cycle values. The
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/linux/Documentation/devicetree/bindings/regulator/
H A Dpwm-regulator.yaml19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
29 appropriate duty-cycle values. This allows for a much more fine grained
31 make an assumption that a %50 duty-cycle value will cause the regulator
49 description: Voltage and Duty-Cycle table.
54 - description: duty-cycle in percent (%)
63 Integer value encoding the duty cycle unit. If not
75 Duty cycle values are expressed in pwm-dutycycle-unit.
104 * Inverted PWM logic, and the duty cycle range is limited
119 /* Voltage Duty
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/linux/Documentation/devicetree/bindings/input/
H A Dpwm-vibrator.yaml14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
39 direction-duty-cycle-ns:
41 Duty cycle of the direction PWM channel in nanoseconds,
58 direction-duty-cycle-ns = <1000000000>;
/linux/drivers/hwmon/
H A Dasus_rog_ryujin.c51 /* Cooler duty report offsets */
61 /* Controller duty report offsets */
118 u8 duty_input[3]; /* Pump, internal fan and controller fan duty in PWM */
239 /* Retrieve cooler duty */ in rog_ryujin_get_status()
247 /* Retrieve controller duty */ in rog_ryujin_get_status()
315 * Retrieve cooler duty since both pump and internal fan are set in rog_ryujin_write_fixed_duty()
331 /* Cooler pump duty */ in rog_ryujin_write_fixed_duty()
336 /* Cooler internal fan duty */ in rog_ryujin_write_fixed_duty()
345 * Controller fan duty (channel == 2). No need to retrieve current in rog_ryujin_write_fixed_duty()
346 * duty, so just send the command. in rog_ryujin_write_fixed_duty()
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/linux/include/trace/events/
H A Dclk.h233 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
235 TP_ARGS(core, duty),
245 __entry->num = duty->num;
246 __entry->den = duty->den;
255 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
257 TP_ARGS(core, duty)
262 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
264 TP_ARGS(core, duty)
/linux/drivers/leds/rgb/
H A Dleds-pwm-multicolor.c35 unsigned long long duty; in led_pwm_mc_set() local
44 duty = priv->leds[i].state.period; in led_pwm_mc_set()
45 duty *= mc_cdev->subled_info[i].brightness; in led_pwm_mc_set()
46 do_div(duty, cdev->max_brightness); in led_pwm_mc_set()
49 duty = priv->leds[i].state.period - duty; in led_pwm_mc_set()
51 priv->leds[i].state.duty_cycle = duty; in led_pwm_mc_set()
/linux/drivers/clk/
H A Dclk-scmi.c139 static int scmi_clk_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) in scmi_clk_get_duty_cycle() argument
149 duty->num = val; in scmi_clk_get_duty_cycle()
150 duty->den = 100; in scmi_clk_get_duty_cycle()
153 "Failed to get duty cycle for clock ID %d\n", clk->id); in scmi_clk_get_duty_cycle()
159 static int scmi_clk_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) in scmi_clk_set_duty_cycle() argument
165 /* SCMI OEM Duty Cycle is expressed as a percentage */ in scmi_clk_set_duty_cycle()
166 val = (duty->num * 100) / duty->den; in scmi_clk_set_duty_cycle()
172 "Failed to set duty cycle(%u/%u) for clock ID %d\n", in scmi_clk_set_duty_cycle()
173 duty->num, duty->den, clk->id); in scmi_clk_set_duty_cycle()
256 /* Duty cycle */ in scmi_clk_ops_alloc()
/linux/Documentation/driver-api/thermal/
H A Dcpu-idle-cooling.rst71 or decreased by modulating the duty cycle of the idle injection.
86 duty cycle 25%
90 the duty cycle percentage. When no mitigation is happening the cooling
91 device state is zero, meaning the duty cycle is 0%.
94 starting state is selected. With a fixed idle duration and the duty
98 The governor will change the cooling device state thus the duty cycle
114 duty cycle 33%
128 duty cycle 50%
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
H A Dgk104.c43 u32 div, duty; in gk104_volt_get() local
46 duty = nvkm_rd32(device, 0x20344); in gk104_volt_get()
48 return bios->base + bios->pwm_range * duty / div; in gk104_volt_get()
56 u32 div, duty; in gk104_volt_set() local
60 duty = DIV_ROUND_UP((uv - bios->base) * div, bios->pwm_range); in gk104_volt_set()
63 nvkm_wr32(device, 0x20344, 0x80000000 | duty); in gk104_volt_set()
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_led.c42 u32 div, duty; in nouveau_led_get_brightness() local
45 duty = nvif_rd32(device, 0x61c884) & 0x00ffffff; in nouveau_led_get_brightness()
48 return duty * LED_FULL / div; in nouveau_led_get_brightness()
62 u32 div, duty; in nouveau_led_set_brightness() local
65 duty = value * div / LED_FULL; in nouveau_led_set_brightness()
73 nvif_wr32(device, 0x61c884, 0xc0000000 | duty); in nouveau_led_set_brightness()

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