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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-dsp-keystone.txt1 Keystone 2 DSP GPIO controller bindings
3 HOST OS userland running on ARM can send interrupts to DSP cores using
4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
7 For example TCI6638K2K SoC has 8 DSP GPIO controllers:
8 - 8 for C66x CorePacx CPUs 0-7
10 Keystone 2 DSP GPIO controller has specific features:
11 - each GPIO can be configured only as output pin;
12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
13 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
17 - compatible: should be "ti,keystone-dsp-gpio"
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H A Dti,keystone-dsp-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Keystone 2 DSP GPIO controller
10 - Grygorii Strashko <grygorii.strashko@ti.com>
13 HOST OS userland running on ARM can send interrupts to DSP cores using
14 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
17 For example TCI6638K2K SoC has 8 DSP GPIO controllers:
18 - 8 for C66x CorePacx CPUs 0-7
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of various
26 [2] Pinctrl: ../pinctrl/pinctrl-bindings.txt
29 [3] include/dt-bindings/pinctrl/lochnagar.h
37 - cirrus,lochnagar-pinctrl
39 gpio-controller: true
41 '#gpio-cells':
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dti,keystone-irq.txt1 Keystone 2 IRQ controller IP
3 On Keystone SOCs, DSP cores can send interrupts to ARM
4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
5 The IRQ handler running on HOST OS can identify DSP signal source by
10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
24 compatible = "ti,keystone-irq";
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H A Dti,keystone-irq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ti,keystone-irq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Keystone 2 IRQ controller IP
10 - Grygorii Strashko <grygorii.strashko@ti.com>
13 On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ
14 controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on
15 HOST OS can identify DSP signal source by analyzing SRCCx bits in IPCARx
21 const: ti,keystone-irq
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/freebsd/sys/contrib/device-tree/Bindings/dsp/
H A Dmediatek,mt8195-dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek mt8195 DSP core
10 - YC Hung <yc.hung@mediatek.com>
13 Some boards from mt8195 contain a DSP core used for
14 advanced pre- and post- audio processing.
18 const: mediatek,mt8195-dsp
22 - description: Address and size of the DSP Cfg registers
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/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dcix,sky1-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/cix,sky1-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guomin Chen <Guomin.Chen@cixtech.com>
15 within the SoC, such as the AP, PM, audio DSP, SensorHub MCU,
19 typically used in pairs-one for receiving and one for transmitting.
22 channel 0-7 - Fast channel with 32bit transmit register and IRQ support
23 channel 8 - Doorbell mode,using the mailbox as an interrupt-generating
25 channel 9 - Fifo based channel with 32*32bit depth fifo and IRQ support
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsso
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dqcom,lpass-cpu.txt3 This node models the Qualcomm Technologies Low-Power Audio SubSystem (LPASS).
7 - compatible : "qcom,lpass-cpu" or "qcom,apq8016-lpass-cpu"
8 - clocks : Must contain an entry for each entry in clock-names.
9 - clock-names : A list which must include the following entries:
10 * "ahbix-clk"
11 * "mi2s-osr-clk"
12 * "mi2s-bit-clk"
13 : required clocks for "qcom,lpass-cpu-apq8016"
14 * "ahbix-clk"
15 * "mi2s-bit-clk0"
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H A Dqcom,lpass-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,lpass-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Rohit kumar <quic_rohkumar@quicinc.com>
14 Qualcomm Technologies Inc. SOC Low-Power Audio SubSystem (LPASS) that consist
16 is a module to configure Low-Power Audio Interface(LPAIF) core registers
22 - qcom,lpass-cpu
23 - qcom,apq8016-lpass-cpu
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/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j722s-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clk-0 {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <0>;
21 compatible = "ti,am64-wiz-10g";
23 #address-cells = <1>;
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/omap.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <0>;
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H A Domap4-panda-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com/
5 #include <dt-bindings/input/input.h>
7 #include "omap4-mcpdm.dtsi"
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
20 dsp_memory_region: dsp-memory@98000000 {
21 compatible = "shared-dma-pool";
27 ipu_memory_region: ipu-memory@98800000 {
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/freebsd/sys/contrib/device-tree/Bindings/input/
H A Dcirrus,cs40l50.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - James Ogletree <jogletre@opensource.cirrus.com>
14 integrated DSP, and closed-loop algorithms.
19 - cirrus,cs40l50
27 reset-gpios:
30 vdd-a-supply:
33 vdd-p-supply:
34 description: Power supply for always-on circuits.
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/freebsd/sys/dev/sound/pci/
H A Dcsapcm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
80 /* -------------------------------------------------------------------- */
118 /* -------------------------------------------------------------------- */
125 old = csa->active; in csa_active()
126 csa->active += run; in csa_active()
128 if ((csa->active > 1) || (csa->active < -1)) in csa_active()
129 csa->active = 0; in csa_active()
130 if (csa->card->active) in csa_active()
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H A Dmaestro3.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 * Maestro-3/Allegro FreeBSD pcm sound driver
34 * (+) /dev/dsp multiple concurrent play channels.
35 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit).
37 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel
39 * (-) hardware volme controls don't work =-(
40 * (-) setblocksize() does nothing.
50 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference.
51 * <taku@cent.saitama-u.ac.jp>
[all …]
H A Demu10kx.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2003-2007 Yuriy Tsibizov <yuriy.tsibizov@gfk.ru>
96 #define GPR(i) (sc->gpr_base+(i))
97 #define INP(i) (sc->input_base+(i))
98 #define OUTP(i) (sc->output_base+(i))
100 #define FX2(i) (sc->efxc_base+(i))
101 #define DSP_CONST(i) (sc->dsp_zero+(i))
160 /* Live! 5.1 Digital, non-standard 5.1 (center & sub) outputs */
305 uint32_t(*irq_func) (void *softc, uint32_t irq);
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/freebsd/share/man/man4/
H A Dpcm.42 .\" Copyright (c) 2009-2011 Joel Dahl <joel@FreeBSD.org>
39 .Bd -ragged -offset indent
60 driver are: multichannel audio, per-application
74 .Bl -bullet -compact
118 .Xr snd_uaudio 4 (auto-loaded on device plug)
145 .Bl -tag -width ".Va snd_driver_load" -offset indent
177 re-routing of channels.
198 Commonly used for ear-candy or frequency compensation due to the vast
232 .Bl -tag -width indent
255 .Bl -tag -width indent
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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dqcom,qcs404-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 firmware on the Qualcomm DSP Hexagon cores.
19 - qcom,qcs404-adsp-pas
20 - qcom,qcs404-cdsp-pas
21 - qcom,qcs404-wcss-pas
28 - description: XO clock
[all …]
H A Dqcom,sm6115-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm6115-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konradybcio@kernel.org>
15 firmware on the Qualcomm DSP Hexagon cores.
20 - enum:
21 - qcom,sm6115-adsp-pas
22 - qcom,sm6115-cdsp-pas
[all …]
H A Dqcom,sc8280xp-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc8280xp-pas.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dqcom,sm6350-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm6350-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 firmware on the Qualcomm DSP Hexagon cores.
19 - qcom,sm6350-adsp-pas
20 - qcom,sm6350-cdsp-pas
21 - qcom,sm6350-mpss-pas
28 - description: XO clock
[all …]
H A Dqcom,sa8775p-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sa8775p-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
14 on the Qualcomm DSP Hexagon cores.
19 - items:
20 - enum:
21 - qcom,qcs8300-adsp-pas
22 - const: qcom,sa8775p-adsp-pas
[all …]
H A Dqcom,sc7180-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 firmware on the Qualcomm DSP Hexagon cores.
19 - qcom,sc7180-adsp-pas
20 - qcom,sc7180-mpss-pas
21 - qcom,sc7280-adsp-pas
22 - qcom,sc7280-cdsp-pas
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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