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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dsi.c238 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) in mtk_dsi_mask() argument
240 u32 temp = readl(dsi->regs + offset); in mtk_dsi_mask()
242 writel((temp & ~mask) | (data & mask), dsi->regs + offset); in mtk_dsi_mask()
245 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) in mtk_dsi_phy_timconfig() argument
248 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ); in mtk_dsi_phy_timconfig()
249 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig()
286 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); in mtk_dsi_phy_timconfig()
287 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); in mtk_dsi_phy_timconfig()
288 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2); in mtk_dsi_phy_timconfig()
289 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3); in mtk_dsi_phy_timconfig()
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/linux/drivers/gpu/drm/sun4i/
H A Dsun6i_mipi_dsi.c291 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi) in sun6i_dsi_inst_abort() argument
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
297 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi) in sun6i_dsi_inst_commit() argument
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
304 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi) in sun6i_dsi_inst_wait_for_completion() argument
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
314 static void sun6i_dsi_inst_setup(struct sun6i_dsi *dsi, in sun6i_dsi_inst_setup() argument
321 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id), in sun6i_dsi_inst_setup()
329 static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi, in sun6i_dsi_inst_init() argument
334 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LP11, DSI_INST_MODE_STOP, in sun6i_dsi_inst_init()
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/linux/drivers/gpu/drm/stm/
H A Ddw_mipi_dsi-stm.c28 /* DSI digital registers & bit definitions */
32 /* DSI wrapper registers & bit definitions */
35 #define WCFGR_DSIM BIT(0) /* DSI Mode */
39 #define WCR_DSIEN BIT(3) /* DSI ENable */
63 /* dsi color format coding according to the datasheet */
86 struct dw_mipi_dsi *dsi; member
94 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) in dsi_write() argument
96 writel(val, dsi->base + reg); in dsi_write()
99 static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg) in dsi_read() argument
101 return readl(dsi->base + reg); in dsi_read()
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/linux/Documentation/devicetree/bindings/display/
H A Dmipi-dsi-bus.txt1 MIPI DSI (Display Serial Interface) busses
6 define the syntax used to represent a DSI bus in a device tree.
8 This document describes DSI bus-specific properties only or defines existing
9 standard properties in the context of the DSI bus.
11 Each DSI host provides a DSI bus. The DSI host controller's node contains a
15 The following assumes that only a single peripheral is connected to a DSI
18 DSI host
22 a DSI host, the following properties apply to a node representing a DSI host.
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
34 conjunction with another DSI host to drive the same peripheral. Hardware
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H A Dallwinner,sun6i-a31-mipi-dsi.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
7 title: Allwinner A31 MIPI-DSI Controller
17 - allwinner,sun6i-a31-mipi-dsi
18 - allwinner,sun50i-a64-mipi-dsi
19 - allwinner,sun50i-a100-mipi-dsi
21 - const: allwinner,sun20i-d1-mipi-dsi
22 - const: allwinner,sun50i-a100-mipi-dsi
44 vcc-dsi-supply:
45 description: VCC-DSI power supply of the DSI encoder
70 - $ref: dsi-controller.yaml#
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H A Dst,stm32-dsi.yaml4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
7 title: STMicroelectronics STM32 DSI host controller
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
29 - description: DSI bus clock
47 phy-dsi-supply:
58 DSI input port node, connected to the ltdc rgb output port.
64 DSI output port node, connected to a panel or a bridge input port.
91 dsi: dsi@5a000000 {
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H A Dbrcm,bcm2835-dsi0.yaml7 title: Broadcom VC4 (VideoCore4) DSI Controller
13 - $ref: dsi-controller.yaml#
30 - description: The DSI PLL clock feeding the DSI analog PHY
31 - description: The DSI ESC clock
32 - description: The DSI pixel clock
43 # - description: The DSI byte clock for the PHY
44 # - description: The DSI DDR2 clock
45 # - description: The DSI DDR clock
68 dsi1: dsi@7e700000 {
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddsi.c3 * linux/drivers/video/omap2/dss/dsi.c
9 #define DSS_SUBSYS_NAME "DSI"
47 /* DSI Protocol Engine */
213 /* DSI PLL HSDIV indices */
435 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); in dsi_write_reg() local
439 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
440 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
441 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
451 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); in dsi_read_reg() local
455 case DSI_PROTO: base = dsi->proto_base; break; in dsi_read_reg()
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/linux/drivers/gpu/drm/panel/
H A Dpanel-jdi-lt070me05000.c31 struct mipi_dsi_device *dsi; member
50 struct mipi_dsi_device *dsi = jdi->dsi; in jdi_panel_init() local
51 struct device *dev = &jdi->dsi->dev; in jdi_panel_init()
54 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in jdi_panel_init()
56 ret = mipi_dsi_dcs_soft_reset(dsi); in jdi_panel_init()
62 ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT << 4); in jdi_panel_init()
68 ret = mipi_dsi_dcs_set_column_address(dsi, 0, jdi->mode->hdisplay - 1); in jdi_panel_init()
74 ret = mipi_dsi_dcs_set_page_address(dsi, 0, jdi->mode->vdisplay - 1); in jdi_panel_init()
86 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, in jdi_panel_init()
94 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_POWER_SAVE, in jdi_panel_init()
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H A Dpanel-startek-kd070fhfid015.c43 struct mipi_dsi_device *dsi; member
54 struct mipi_dsi_device *dsi = stk->dsi; in stk_panel_init() local
55 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in stk_panel_init()
83 struct mipi_dsi_device *dsi = stk->dsi; in stk_panel_on() local
84 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in stk_panel_on()
95 struct mipi_dsi_device *dsi = stk->dsi; in stk_panel_off() local
96 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in stk_panel_off()
98 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; in stk_panel_off()
195 struct mipi_dsi_device *dsi = bl_get_data(bl); in dsi_dcs_bl_get_brightness() local
199 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; in dsi_dcs_bl_get_brightness()
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H A Dpanel-novatek-nt37801.c22 struct mipi_dsi_device *dsi; member
57 struct mipi_dsi_device *dsi = ctx->dsi; in novatek_nt37801_on() local
58 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in novatek_nt37801_on()
60 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in novatek_nt37801_on()
114 struct mipi_dsi_device *dsi = ctx->dsi; in novatek_nt37801_off() local
115 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in novatek_nt37801_off()
117 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; in novatek_nt37801_off()
131 struct device *dev = &ctx->dsi->dev; in novatek_nt37801_prepare()
148 ret = mipi_dsi_picture_parameter_set(ctx->dsi, &pps); in novatek_nt37801_prepare()
154 ret = mipi_dsi_compression_mode(ctx->dsi, true); in novatek_nt37801_prepare()
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H A Dpanel-samsung-s6e63m0-dsi.c3 * DSI interface to the Samsung S6E63M0 panel.
22 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in s6e63m0_dsi_dcs_read() local
25 ret = mipi_dsi_dcs_read(dsi, cmd, data, 1); in s6e63m0_dsi_dcs_read()
31 dev_dbg(dev, "DSI read CMD %02x = %02x\n", cmd, *data); in s6e63m0_dsi_dcs_read()
39 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in s6e63m0_dsi_dcs_write() local
47 dev_dbg(dev, "DSI writing dcs seq: %*ph\n", (int)len, data); in s6e63m0_dsi_dcs_write()
59 ret = mipi_dsi_dcs_write(dsi, cmd, seqp, chunk); in s6e63m0_dsi_dcs_write()
71 ret = mipi_dsi_dcs_write(dsi, MCS_GLOBAL_PARAM, &cmdwritten, 1); in s6e63m0_dsi_dcs_write()
77 ret = mipi_dsi_dcs_write(dsi, cmd, seqp, chunk); in s6e63m0_dsi_dcs_write()
92 static int s6e63m0_dsi_probe(struct mipi_dsi_device *dsi) in s6e63m0_dsi_probe() argument
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H A Dpanel-osd-osd101t2587-53ts.c20 struct mipi_dsi_device *dsi; member
37 ret = mipi_dsi_shutdown_peripheral(osd101t2587->dsi); in osd101t2587_panel_disable()
63 ret = mipi_dsi_turn_on_peripheral(osd101t2587->dsi); in osd101t2587_panel_enable()
128 struct device *dev = &osd101t2587->dsi->dev; in osd101t2587_panel_add()
144 static int osd101t2587_panel_probe(struct mipi_dsi_device *dsi) in osd101t2587_panel_probe() argument
150 id = of_match_node(osd101t2587_of_match, dsi->dev.of_node); in osd101t2587_panel_probe()
154 dsi->lanes = 4; in osd101t2587_panel_probe()
155 dsi->format = MIPI_DSI_FMT_RGB888; in osd101t2587_panel_probe()
156 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | in osd101t2587_panel_probe()
161 osd101t2587 = devm_drm_panel_alloc(&dsi->dev, __typeof(*osd101t2587), base, in osd101t2587_panel_probe()
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H A Dpanel-panasonic-vvx10f034n00.c31 struct mipi_dsi_device *dsi; member
47 return mipi_dsi_turn_on_peripheral(wuxga_nt->dsi); in wuxga_nt_panel_on()
54 return mipi_dsi_shutdown_peripheral(wuxga_nt->dsi); in wuxga_nt_panel_disable()
160 struct device *dev = &wuxga_nt->dsi->dev; in wuxga_nt_panel_add()
184 static int wuxga_nt_panel_probe(struct mipi_dsi_device *dsi) in wuxga_nt_panel_probe() argument
189 dsi->lanes = 4; in wuxga_nt_panel_probe()
190 dsi->format = MIPI_DSI_FMT_RGB888; in wuxga_nt_panel_probe()
191 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | in wuxga_nt_panel_probe()
196 wuxga_nt = devm_drm_panel_alloc(&dsi->dev, __typeof(*wuxga_nt), base, in wuxga_nt_panel_probe()
203 mipi_dsi_set_drvdata(dsi, wuxga_nt); in wuxga_nt_panel_probe()
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H A Dpanel-sharp-lq101r1sx01.c21 /* the datasheet refers to them as DSI-LINK1 and DSI-LINK2 */
48 struct mipi_dsi_device *dsi = sharp->link1; in sharp_panel_write() local
51 err = mipi_dsi_generic_write(dsi, payload, sizeof(payload)); in sharp_panel_write()
53 dev_err(&dsi->dev, "failed to write %02x to %04x: %zd\n", in sharp_panel_write()
58 err = mipi_dsi_dcs_nop(dsi); in sharp_panel_write()
60 dev_err(&dsi->dev, "failed to send DCS nop: %zd\n", err); in sharp_panel_write()
198 * put in place to communicate the configuration back to the DSI host in sharp_panel_prepare()
300 static int sharp_panel_probe(struct mipi_dsi_device *dsi) in sharp_panel_probe() argument
307 dsi->lanes = 4; in sharp_panel_probe()
308 dsi->format = MIPI_DSI_FMT_RGB888; in sharp_panel_probe()
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H A Dpanel-raspberrypi-touchscreen.c36 * TC358762XBG DSI-DPI bridge, and an I2C-connected Atmel ATTINY88-MUR
40 * This driver controls the TC358762 and ATTINY88, presenting a DSI
58 #define RPI_DSI_DRIVER_NAME "rpi-ts-dsi"
83 /* DSI D-PHY Layer Registers */
94 /* DSI PPI Layer Registers */
118 /* DSI Protocol Layer Registers */
140 /* DSI General Registers */
144 /* DSI Application Layer Registers */
193 struct mipi_dsi_device *dsi; member
245 mipi_dsi_generic_write(ts->dsi, msg, sizeof(msg)); in rpi_touchscreen_write()
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-dsi.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
20 - nvidia,tegra124-dsi
21 - nvidia,tegra210-dsi
22 - nvidia,tegra186-dsi
25 - const: nvidia,tegra132-dsi
26 - const: nvidia,tegra124-dsi
48 - const: dsi
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi.yaml4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
13 This binding describes the MIPI DSI encoder embedded in the Renesas
14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
18 - $ref: /schemas/display/dsi-controller.yaml#
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
25 - renesas,r9a07g054-mipi-dsi # RZ/V2L
26 - const: renesas,rzg2l-mipi-dsi
36 - description: DSI Packet Receive interrupt
37 - description: DSI Fatal Error interrupt
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H A Drenesas,dsi-csi2-tx.yaml4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder
13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
20 - renesas,r8a779a0-dsi-csi2-tx # for V3U
21 - renesas,r8a779g0-dsi-csi2-tx # for V4H
22 - renesas,r8a779h0-dsi-csi2-tx # for V4M
30 - description: DSI (and CSI-2) functional clock
36 - const: dsi
56 description: DSI/CSI-2 output port
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H A Dcdns,dsi.yaml4 $id: http://devicetree.org/schemas/display/bridge/cdns,dsi.yaml#
7 title: Cadence DSI bridge
13 CDNS DSI is a bridge device which converts DPI to DSI
18 - cdns,dsi
19 - ti,j721e-dsi
61 Output port representing the DSI output. It can have
63 the DSI virtual channel used by this device.
74 - $ref: ../dsi-controller.yaml#
80 const: ti,j721e-dsi
111 dsi@fd0c0000 {
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H A Dnwl-dsi.yaml4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
22 const: fsl,imx8mq-nwl-dsi
42 - description: DSI core clock
74 - description: dsi byte reset line
75 - description: dsi dpi reset line
76 - description: dsi esc reset line
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/linux/Documentation/devicetree/bindings/display/msm/
H A Ddsi-phy-14nm.yaml4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
7 title: Qualcomm Display DSI 14nm PHY
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-14nm
19 - qcom,dsi-phy-14nm-2290
20 - qcom,dsi-phy-14nm-660
21 - qcom,dsi-phy-14nm-8953
22 - qcom,sm6125-dsi-phy-14nm
23 - qcom,sm6150-dsi-phy-14nm
27 - description: dsi phy register set
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/linux/drivers/video/fbdev/omap2/omapfb/displays/
H A Dpanel-dsi-cm.c3 * Generic DSI Command Mode panel driver
28 /* DSI Virtual channel. Hardcoded for now. */
112 r = in->ops.dsi->dcs_read(in, ddata->channel, dcs_cmd, buf, 1); in dsicm_dcs_read_1()
125 return in->ops.dsi->dcs_write(in, ddata->channel, &dcs_cmd, 1); in dsicm_dcs_write_0()
133 return in->ops.dsi->dcs_write(in, ddata->channel, buf, 2); in dsicm_dcs_write_1()
146 r = in->ops.dsi->dcs_write_nosync(in, ddata->channel, &cmd, 1); in dsicm_sleep_in()
208 r = in->ops.dsi->dcs_write_nosync(in, ddata->channel, buf, sizeof(buf)); in dsicm_set_update_window()
218 r = in->ops.dsi->dcs_write_nosync(in, ddata->channel, buf, sizeof(buf)); in dsicm_set_update_window()
222 in->ops.dsi->bta_sync(in, ddata->channel); in dsicm_set_update_window()
256 in->ops.dsi->disable(in, false, true); in dsicm_enter_ulps()
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/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-dsi-j721e.c3 * TI j721e Cadence DSI wrapper
12 #include "cdns-dsi-j721e.h"
23 static int cdns_dsi_j721e_init(struct cdns_dsi *dsi) in cdns_dsi_j721e_init() argument
25 struct platform_device *pdev = to_platform_device(dsi->base.dev); in cdns_dsi_j721e_init()
27 dsi->j721e_regs = devm_platform_ioremap_resource(pdev, 1); in cdns_dsi_j721e_init()
28 return PTR_ERR_OR_ZERO(dsi->j721e_regs); in cdns_dsi_j721e_init()
31 static void cdns_dsi_j721e_enable(struct cdns_dsi *dsi) in cdns_dsi_j721e_enable() argument
35 * to DSI DPI0. This is the only supported configuration on in cdns_dsi_j721e_enable()
38 writel(DSI_WRAP_DPI_0_EN, dsi->j721e_regs + DSI_WRAP_DPI_CONTROL); in cdns_dsi_j721e_enable()
41 static void cdns_dsi_j721e_disable(struct cdns_dsi *dsi) in cdns_dsi_j721e_disable() argument
[all …]
/linux/Documentation/devicetree/bindings/display/panel/
H A Dsharp,lq101r1sx01.yaml13 This panel requires a dual-channel DSI host to operate. It supports two modes:
17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1), left or even, is considered the primary
20 to the peripheral driven by the second link (DSI-LINK2, right or odd).
22 Note that in video mode the DSI-LINK1 interface always provides the left/even
23 pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it
49 phandle to the DSI peripheral on the secondary link. Note that the
50 presence of this property marks the containing node as DSI-LINK1
67 dsi0: dsi@fd922800 {
83 dsi1: dsi@fd922a00 {

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