Searched +full:dsi +full:- +full:phy +full:- +full:10 +full:nm +full:- +full:8998 (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree17 $ref: /schemas/display/msm/mdss-common.yaml#21 const: qcom,msm8998-mdss25 - description: Display AHB clock26 - description: Display AXI clock[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 #include <linux/clk-provider.h>10 #include <dt-bindings/phy/phy.h>15 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))22 v = (tmax - tmin) * percent; in linear_inter()25 return max_t(s32, min_result, v - 1); in linear_inter()37 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()38 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()48 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()49 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()[all …]