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/linux/arch/arm/boot/dts/samsung/
H A Dexynos4x12-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
24 #gpio-cells = <2>;
[all …]
H A Ds5pv210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source - pin control-related
6 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are
15 #include "s5pv210-pinctrl.h"
18 pin- ## _pin { \
20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \
21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \
25 gpa0: gpa0-gpio-bank {
26 gpio-controller;
[all …]
H A Dexynos5250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
[all …]
H A Dexynos4210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device
14 #include "exynos-pinctrl.h"
17 gpa0: gpa0-gpio-bank {
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
[all …]
H A Dexynos5420-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpy7: gpy7-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpx0: gpx0-gpio-bank {
[all …]
H A Dexynos3250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \
23 pin- ## _pin { \
25 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
[all …]
H A Dexynos5260-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
[all …]
H A Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
20 gpa1: gpa1-gpio-bank {
21 gpio-controller;
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
29 PIN(_pin, 2, _pull, _drv)
32 gpa0: gpa0-gpio-bank {
[all …]
H A Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
[all …]
H A Dexynos7885-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 etc0: etc0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
[all …]
H A Dexynos850-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 gpa0: gpa0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
[all …]
H A Dexynosautov9-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
11 #include "exynos-pinctrl.h"
14 gpa0: gpa0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
[all …]
/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * GS101 SoC pin-mux and pin-config device tree source
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include "gs101-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
15 interrupt-controller;
16 #interrupt-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drockchip-pinconf.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /omit-if-no-ref/
8 pcfg_pull_up: pcfg-pull-up {
9 bias-pull-up;
12 /omit-if-no-ref/
13 pcfg_pull_down: pcfg-pull-down {
14 bias-pull-down;
17 /omit-if-no-ref/
18 pcfg_pull_none: pcfg-pull-none {
19 bias-disable;
[all …]
/linux/arch/arm64/boot/dts/tesla/
H A Dfsd-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2021 Tesla, Inc.
11 #include "fsd-pinctrl.h"
14 gpf0: gpf0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
18 interrupt-controller;
19 #interrupt-cells = <2>;
[all …]
/linux/drivers/phy/renesas/
H A Dphy-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car Gen2 PHY driver
32 /* USB General control register 2 (UGCTRL2) */
45 #define PHYS_PER_CHANNEL 2
56 struct rcar_gen2_phy_driver *drv; member
79 struct rcar_gen2_channel *channel = phy->channel; in rcar_gen2_phy_init()
80 struct rcar_gen2_phy_driver *drv = channel->drv; in rcar_gen2_phy_init() local
88 * driver. Achieving this with cmpxcgh() should be SMP-safe. in rcar_gen2_phy_init()
90 if (cmpxchg(&channel->selected_phy, -1, phy->number) != -1) in rcar_gen2_phy_init()
91 return -EBUSY; in rcar_gen2_phy_init()
[all …]
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,rpmh-rsc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
22 be written to from Linux. The structure of each DRV follows the same template
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
29 WAKE - Triggered by F/W
[all …]
/linux/drivers/pmdomain/qcom/
H A Dcpr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
27 #include <linux/nvmem-consumer.h>
29 /* Register Offsets for RB-CPR and Bit Definitions */
98 #define RBCPR_RESULT0_ERROR_STEPS_SHIFT 2
109 #define CPR_INT_DOWN BIT(2)
125 #define FUSE_REVISION_UNKNOWN (-1)
252 static bool cpr_is_allowed(struct cpr_drv *drv) in cpr_is_allowed() argument
254 return !drv->loop_disabled; in cpr_is_allowed()
257 static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value) in cpr_write() argument
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-drv.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
8 #include <linux/dma-mapping.h>
13 #include "iwl-drv.h"
14 #include "iwl-csr.h"
15 #include "iwl-debug.h"
16 #include "iwl-trans.h"
17 #include "iwl-op-mode.h"
[all …]
/linux/drivers/cpuidle/governors/
H A Dteo.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018 - 2021 Intel Corporation
10 * DOC: teo-description
22 * Of course, non-timer wakeup sources are more important in some use cases
39 * idle state 2, the third bin spans from the target residency of idle state 2
62 * the current sleep length (the candidate idle state) and compute 2 sums as
65 * - The sum of the "hits" and "intercepts" metrics for the candidate state
70 * - The sum of the "intercepts" metrics for all of the idle states shallower
75 * 2. If the second sum is greater than the first one the CPU is likely to wake
78 * - Traverse the idle states shallower than the candidate one in the
[all …]
/linux/drivers/cpufreq/
H A Dqcom-cpufreq-nvmem.c1 // SPDX-License-Identifier: GPL-2.0
10 * defines the voltage and frequency value based on the msm-id in SMEM
12 * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
15 * operating-points-v2 table when it is parsed by the OPP framework.
23 #include <linux/nvmem-consumer.h>
33 #include <dt-bindings/arm/qcom,ids.h>
41 #define IPQ6000_VERSION BIT(2)
54 struct qcom_cpufreq_drv *drv);
74 struct qcom_cpufreq_drv *drv) in qcom_cpufreq_simple_get_version() argument
84 drv->versions = 1 << *speedbin; in qcom_cpufreq_simple_get_version()
[all …]
/linux/drivers/watchdog/
H A Dmena21_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
42 static unsigned int a21_wdt_get_bootstatus(struct a21_wdt_drv *drv) in a21_wdt_get_bootstatus() argument
46 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST0]) ? (1 << 0) : 0; in a21_wdt_get_bootstatus()
47 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST1]) ? (1 << 1) : 0; in a21_wdt_get_bootstatus()
48 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST2]) ? (1 << 2) : 0; in a21_wdt_get_bootstatus()
55 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_start() local
57 gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 1); in a21_wdt_start()
64 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_stop() local
66 gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 0); in a21_wdt_stop()
73 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_ping() local
[all …]
/linux/drivers/phy/samsung/
H A Dphy-exynos5250-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
13 #include "phy-samsung-usb2.h"
49 #define EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST BIT(2)
69 #define EXYNOS_5250_HSICPHYCTRLX_UTMISWRST BIT(2)
114 #define EXYNOS_5250_USBOTGSYS_OTGDISABLE BIT(2)
168 return -EINVAL; in exynos5250_rate_to_clk()
176 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos5250_isol() local
180 if (drv->cfg == &exynos5250_usb2_phy_config && in exynos5250_isol()
181 inst->cfg->id == EXYNOS5250_DEVICE) in exynos5250_isol()
[all …]
/linux/drivers/soc/qcom/
H A Drpmh-internal.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
26 * @drv: The controller.
27 * @type: Type of the TCS in this group - active, sleep, wake.
35 * Start: grab drv->lock, set req, set tcs_in_use, drop drv->lock,
38 * grab drv->lock, clear tcs_in_use, drop drv->lock
41 * case that (ncpt < MAX_CMDS_PER_TCS). That is if ncpt = 2 and
42 * MAX_CMDS_PER_TCS = 16 then bit[2] = the first bit in 2nd TCS.
45 struct rsc_drv *drv; member
56 * struct rpmh_request: the message to be sent to rpmh-rsc
[all …]

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