| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | pinctrl-mt8183.txt | 6 - compatible: value should be one of the following.
7 "mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
8 - gpio-controller : Marks the device node as a gpio controller.
9 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
12 - gpio-ranges : gpio valid number range.
13 - reg: physical address base for gpio base registers. There are 10 GPIO
17 - reg-names: gpio base register names. There are 10 gpio base register
20 - interrupt-controller: Marks the device node as an interrupt controller
21 - #interrupt-cells: Should be two.
22 - interrupts : The interrupt outputs to sysirq.
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| H A D | sprd,pinctrl.txt | 8 pad driving level, system control select and so on ("domain pad
9 driving level": One pin can output 3.0v or 1.8v, depending on the
10 related domain pad driving selection, if the related domain pad
16 of them, so we can not make every Spreadtrum-special configuration
35 - input-enable
36 - input-disabl
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| H A D | mediatek,mt8183-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctr
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| H A D | mediatek,mt8365-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctr
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| H A D | pinctrl-stmfx.txt | 1 STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander bindings
3 ST Multi-Function eXpander (STMFX) offers up to 24 GPIOs expansion.
7 - compatible: should be "st,stmfx-0300-pinctrl".
8 - #gpio-cells: should be <2>, the first cell is the GPIO number and the second
9 cell is the gpio flags in accordance with <dt-bindings/gpio/gpio.h>.
10 - gpio-controller: marks the device as a GPIO controller.
11 - #interrupt-cells: should be <2>, the first cell is the GPIO number and the
13 <dt-bindings/interrupt-controller/irq.h>.
14 - interrupt-controller: marks the device as an interrupt controller.
15 - gpio-ranges: specifies the mapping between gpio controller and pin
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| H A D | pincfg-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 bias-disable:
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
29 bias-bus-hold:
33 bias-pull-up:
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| /freebsd/sys/contrib/device-tree/Bindings/power/reset/ |
| H A D | gpio-restart.txt | 4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
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| H A D | gpio-restart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restar
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| H A D | gpio-poweroff.txt | 3 The driver supports both level triggered and edge triggered power off.
9 When the power-off handler is called, the gpio is configured as an
10 output, and drive active, so triggering a level triggered power off
11 condition. This will also cause an inactive->active edge condition, so
13 the GPIO is set to inactive, thus causing an active->inactive edge,
19 - compatible : should be "gpio-poweroff".
20 - gpios : The GPIO to set high/low, see "gpios property" in
26 - input : Initially configure the GPIO line as an input. Only reconfigure
27 it to an output when the power-off handler is called. If this optional
30 - active-delay-ms: Delay (default 100) to wait after driving gpio active
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| /freebsd/sys/contrib/device-tree/Bindings/leds/backlight/ |
| H A D | richtek,rt4831-backlight.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/richtek,rt4831-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
16 For the LCD backlight, it can provide four channel WLED driving capability.
17 Each channel driving current is up to 30mA
20 https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf
23 - $ref: common.yaml#
27 const: richtek,rt4831-backlight
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| /freebsd/sys/dev/iicbus/ |
| H A D | iic_recover_bus.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 * Helper code to recover a hung i2c bus by bit-banging a recovery sequence.
34 * An i2c bus can be hung by a slave driving the clock (rare) or data lines low.
35 * The most common cause is a partially-completed transaction such as rebooting
37 * freeze for any amount of time, the slave device will continue driving the
42 * Any i2c driver which is able to manually set the level of the clock and data
67 pins->setsda(pins->ctx, 1); in iic_recover_bus()
68 pins->setscl(pins->ctx, 1); in iic_recover_bus()
72 * bus is doing clock-stretching and we should wait a while. If that in iic_recover_bus()
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | cdns,gpio.txt | 4 - compatible: should be "cdns,gpio-r1p02".
5 - reg: the register base address and size.
6 - #gpio-cells: should be 2.
9 <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
11 - gpio-controller: marks the device as a GPIO controller.
12 - clocks: should contain one entry referencing the peripheral clock driving
16 - ngpios: integer number of gpio lines supported by this controller, up to 32.
17 - interrupts: interrupt specifier for the controllers interrupt.
18 - interrupt-controller: marks the device as an interrupt controller. When
19 defined, interrupts, interrupt-parent and #interrupt-cells
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| H A D | nxp,pcf8575.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCF857x-compatible I/O expanders
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
14 driven high by a pull-up current source or driven low to ground. This
15 combines the direction and output level into a single bit per line, which
17 line is configured (a) as output and driving the signal low/high, or (b) as
25 - maxim,max7328
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|
| H A D | gpio-pcf857x.txt | 1 * PCF857x-compatible I/O expanders
3 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
4 driven high by a pull-up current source or driven low to ground. This combines
5 the direction and output level into a single bit per line, which can't be read
7 (a) as output and driving the signal low/high, or (b) as input and reporting a
14 - compatible: should be one of the following.
15 - "maxim,max7328": For the Maxim MAX7378
16 - "maxim,max7329": For the Maxim MAX7329
17 - "nxp,pca8574": For the NXP PCA8574
18 - "nxp,pca8575": For the NXP PCA8575
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | cdns,csi2rx.txt | 1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18 - phys: phandle to the external D-PHY, phy-names must be provided
19 - phy-names: must contain "dphy", if the implementation uses an
20 external D-PHY
[all …]
|
| H A D | cdns,csi2tx.txt | 1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | qcom,usb-snps-femto-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys Femto High-Speed USB PHY V2
10 - Wesley Cheng <quic_wcheng@quicinc.com>
13 Qualcomm High-Speed USB PHY
18 - enum:
19 - qcom,sc8180x-usb-hs-phy
20 - qcom,usb-snps-femto-v2-phy
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|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocBase.h | 1 //===- RegAllocBase.h - basic regalloc interface and driver -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 // - If virtual and physical register liveness is modeled using intervals, then
15 // on-the-fly interference checking is cheap. Furthermore, interferences can be
18 // - Register allocation complexity, and generated code performance is
27 // coloring, instead driving the assignment of virtual to physical registers by
32 // quality trade-off without relying on a particular theoretical solver.
34 //===----------------------------------------------------------------------===//
99 // The top-level driver. The output is a VirtRegMap that us updated with
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| /freebsd/share/doc/psd/05.sysman/ |
| H A D | 1.5.t | 39 introduces a level of indirection, so that descriptors may be shared
140 or other device-specific events have occurred.
161 non-blocking I/O mode and/or enable signaling when I/O is
166 Operations on non-blocking descriptors will
174 be signaled, with a SIGIO for input, output, or in-progress
179 using non-blocking output,
206 Protocols may be based on communications multiplexing or a rights-passing
209 locally generated ``read-ahead'' requests. A protocol that provides for
210 read-ahead may provide higher performance but have a more difficult
213 Another example is the terminal driving facilities. Normally a terminal
|
| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sc7180-trogdor.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/gpio-keys.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulato
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| H A D | sdm845-cheza.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
25 stdout-path = "serial0:115200n8";
29 compatible = "pwm-backlight";
31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32 power-suppl
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| /freebsd/sys/contrib/device-tree/src/arm/axis/ |
| H A D | artpec6.dtsi | 2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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| /freebsd/sys/contrib/device-tree/src/arm64/allwinner/ |
| H A D | sun50i-a64-teres-i.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // based on sun50i-a64-olinuxino.dts by Jagan Teki <jteki@openedev.com>
5 /dts-v1/;
7 #include "sun50i-a64.dtsi"
8 #include "sun50i-a64-cpu-opp.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/pwm/pwm.h>
15 model = "Olimex A64 Teres-I";
16 compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";
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| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | renesas,rz-mtu3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu
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| /freebsd/contrib/ofed/opensm/include/opensm/ |
| H A D | osm_subnet.h | 2 * Copyright (c) 2004-2009 Voltaire, Inc. All rights reserved.
3 * Copyright (c) 2002-2015 Mellanox Technologies LTD. All rights reserved.
4 * Copyright (c) 1996-2003 Intel Corporation. All rights reserved.
9 * Copyright (c) 2009-2015 ZIH, TU Dresden, Federal Republic of Germany. All rights reserved.
21 * - Redistributions of source code must retain the above
25 * - Redistributions in binary form must reproduce the above
139 * table (IBA 7.6.9) (-1 == use default)
447 * If TRUE cause all lids to be re-assigend.
473 * to enter the VLStalled state. This is for switch ports driving
478 * on any port not driving a CA or router port.
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