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/linux/drivers/phy/cadence/
H A Dcdns-dphy.c17 #include <linux/phy/phy-mipi-dphy.h>
23 /* DPHY registers */
88 int (*probe)(struct cdns_dphy *dphy);
89 void (*remove)(struct cdns_dphy *dphy);
90 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
91 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
93 void (*set_pll_cfg)(struct cdns_dphy *dphy,
95 unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
96 int (*wait_for_pll_lock)(struct cdns_dphy *dphy);
97 int (*wait_for_cmn_ready)(struct cdns_dphy *dphy);
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H A Dcdns-dphy-rx.c13 #include <linux/phy/phy-mipi-dphy.h>
82 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_power_on() local
88 dphy->regs + DPHY_CMN_SSM); in cdns_dphy_rx_power_on()
95 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_power_off() local
97 writel(0, dphy->regs + DPHY_CMN_SSM); in cdns_dphy_rx_power_off()
129 static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy_rx *dphy, in cdns_dphy_rx_wait_lane_ready() argument
136 void __iomem *reg = dphy->regs; in cdns_dphy_rx_wait_lane_ready()
172 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_configure() local
183 writel(reg, dphy->regs + DPHY_LANE); in cdns_dphy_rx_configure()
196 writel(reg, dphy->regs + DPHY_BAND_CFG); in cdns_dphy_rx_configure()
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/linux/drivers/phy/allwinner/
H A Dphy-sun6i-mipi-dphy.c18 #include <linux/phy/phy-mipi-dphy.h>
183 void (*tx_power_on)(struct sun6i_dphy *dphy);
202 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_init() local
204 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
205 clk_prepare_enable(dphy->mod_clk); in sun6i_dphy_init()
206 clk_set_rate_exclusive(dphy->mod_clk, 150000000); in sun6i_dphy_init()
213 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_configure() local
220 memcpy(&dphy->config, opts, sizeof(dphy->config)); in sun6i_dphy_configure()
225 static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy) in sun6i_a31_mipi_dphy_tx_power_on() argument
227 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0); in sun6i_a31_mipi_dphy_tx_power_on()
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/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-rx.c3 * StarFive JH7110 DPHY RX driver
75 struct stf_dphy *dphy = phy_get_drvdata(phy); in stf_dphy_configure() local
76 const struct stf_dphy_info *info = dphy->info; in stf_dphy_configure()
88 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188)); in stf_dphy_configure()
93 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(192)); in stf_dphy_configure()
99 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(196)); in stf_dphy_configure()
102 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(200)); in stf_dphy_configure()
109 struct stf_dphy *dphy = phy_get_drvdata(phy); in stf_dphy_power_on() local
112 ret = pm_runtime_resume_and_get(dphy->dev); in stf_dphy_power_on()
116 ret = regulator_enable(dphy->mipi_0p9); in stf_dphy_power_on()
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H A Dphy-jh7110-dphy-tx.c3 * DPHY TX driver for the StarFive JH7110 SoC
19 #include <linux/phy/phy-mipi-dphy.h>
212 static void stf_dphy_hw_reset(struct stf_dphy *dphy, int assert) in stf_dphy_hw_reset() argument
218 dphy->topsys + STF_DPHY_APBIFSAIF_SYSCFG(100)); in stf_dphy_hw_reset()
221 rc = readl_poll_timeout_atomic(dphy->topsys + in stf_dphy_hw_reset()
227 dev_err(dphy->dev, "MIPI dphy-tx # PLL Locked\n"); in stf_dphy_hw_reset()
233 struct stf_dphy *dphy = phy_get_drvdata(phy); in stf_dphy_configure() local
234 const struct stf_dphy_info *info = dphy->info; in stf_dphy_configure()
246 tmp = readl(dphy->topsys + STF_DPHY_APBIFSAIF_SYSCFG(100)); in stf_dphy_configure()
249 writel(tmp, dphy->topsys + STF_DPHY_APBIFSAIF_SYSCFG(100)); in stf_dphy_configure()
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/linux/Documentation/devicetree/bindings/phy/
H A Drockchip-inno-csi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
19 - rockchip,px30-csi-dphy
20 - rockchip,rk1808-csi-dphy
21 - rockchip,rk3326-csi-dphy
22 - rockchip,rk3368-csi-dphy
23 - rockchip,rk3568-csi-dphy
24 - rockchip,rk3588-csi-dphy
75 - rockchip,px30-csi-dphy
76 - rockchip,rk1808-csi-dphy
77 - rockchip,rk3326-csi-dphy
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H A Drockchip,px30-dsi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
7 title: Rockchip MIPI DPHY with additional LVDS/TTL modes
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
21 - rockchip,rk3568-dsi-dphy
22 - rockchip,rv1126-dsi-dphy
63 compatible = "rockchip,px30-dsi-dphy";
H A Dallwinner,sun6i-a31-mipi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - const: allwinner,sun50i-a100-mipi-dphy
22 - const: allwinner,sun50i-a64-mipi-dphy
23 - const: allwinner,sun6i-a31-mipi-dphy
25 - const: allwinner,sun20i-d1-mipi-dphy
26 - const: allwinner,sun50i-a100-mipi-dphy
75 compatible = "allwinner,sun6i-a31-mipi-dphy";
H A Drockchip-mipi-dphy-rx0.yaml4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
19 const: rockchip,rk3399-mipi-dphy-rx0
29 - const: dphy-ref
30 - const: dphy-cfg
65 mipi_dphy_rx0: mipi-dphy-rx0 {
66 compatible = "rockchip,rk3399-mipi-dphy-rx0";
70 clock-names = "dphy-ref", "dphy-cfg", "grf";
H A Dmixel,mipi-dsi-phy.yaml23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
59 const: fsl,imx8mq-mipi-dphy
73 const: fsl,imx8qxp-mipi-dphy
83 dphy: dphy@30a0030 {
84 compatible = "fsl,imx8mq-mipi-dphy";
H A Dcdns,dphy.yaml4 $id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
7 title: Cadence DPHY
15 - cdns,dphy
16 - ti,j721e-dphy
51 compatible = "cdns,dphy";
H A Dcdns,dphy-rx.yaml4 $id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml#
7 title: Cadence DPHY Rx
15 - const: cdns,dphy-rx
38 compatible = "cdns,dphy-rx";
H A Damlogic,axg-mipi-dphy.yaml5 $id: http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#
16 - amlogic,axg-mipi-dphy
61 compatible = "amlogic,axg-mipi-dphy";
H A Dstarfive,jh7110-dphy-tx.yaml4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-tx.yaml#
19 const: starfive,jh7110-dphy-tx
60 compatible = "starfive,jh7110-dphy-tx";
H A Dstarfive,jh7110-dphy-rx.yaml4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
19 const: starfive,jh7110-dphy-rx
61 compatible = "starfive,jh7110-dphy-rx";
/linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
H A Dsun8i_a83t_dphy.c13 static int sun8i_a83t_dphy_configure(struct phy *dphy, in sun8i_a83t_dphy_configure() argument
19 static int sun8i_a83t_dphy_power_on(struct phy *dphy) in sun8i_a83t_dphy_power_on() argument
21 struct sun8i_a83t_mipi_csi2_device *csi2_dev = phy_get_drvdata(dphy); in sun8i_a83t_dphy_power_on()
36 static int sun8i_a83t_dphy_power_off(struct phy *dphy) in sun8i_a83t_dphy_power_off() argument
38 struct sun8i_a83t_mipi_csi2_device *csi2_dev = phy_get_drvdata(dphy); in sun8i_a83t_dphy_power_off()
57 csi2_dev->dphy = devm_phy_create(dev, NULL, &sun8i_a83t_dphy_ops); in sun8i_a83t_dphy_register()
58 if (IS_ERR(csi2_dev->dphy)) { in sun8i_a83t_dphy_register()
60 return PTR_ERR(csi2_dev->dphy); in sun8i_a83t_dphy_register()
63 phy_set_drvdata(csi2_dev->dphy, csi2_dev); in sun8i_a83t_dphy_register()
/linux/drivers/gpu/drm/kmb/
H A Dkmb_regs.h647 #define SET_DPHY_INIT_CTRL0(dev, dphy, offset) \ argument
649 ((dphy) + (offset)))
650 #define CLR_DPHY_INIT_CTRL0(dev, dphy, offset) \ argument
652 ((dphy) + (offset)))
659 #define SET_DPHY_FREQ_CTRL0_3(dev, dphy, val) \ argument
661 + (((dphy) / 4) * 4), (dphy % 4) * 8, 6, val)
667 #define GET_STOPSTATE_DATA(dev, dphy) \ argument
669 ((dphy) / 4) * 4)) >> \
670 (((dphy % 4) * 8) + 4)) & 0x03)
675 #define SET_DPHY_TEST_CTRL0(dev, dphy) \ argument
[all …]
/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-csi.c16 #include <linux/phy/phy-mipi-dphy.h>
171 phy_set_mode(csi->dphy, PHY_MODE_MIPI_DPHY); in rkisp1_csi_start()
172 phy_configure(csi->dphy, &opts); in rkisp1_csi_start()
173 phy_power_on(csi->dphy); in rkisp1_csi_start()
190 phy_power_off(csi->dphy); in rkisp1_csi_stop()
209 * Disable DPHY errctrl interrupt, because this dphy in rkisp1_csi_isr()
222 * Enable DPHY errctrl interrupt again, if mipi have receive in rkisp1_csi_isr()
227 * Enable DPHY errctrl interrupt again, if mipi have receive in rkisp1_csi_isr()
503 csi->dphy = devm_phy_get(rkisp1->dev, "dphy"); in rkisp1_csi_init()
504 if (IS_ERR(csi->dphy)) in rkisp1_csi_init()
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/linux/drivers/phy/amlogic/
H A DKconfig41 tristate "Meson G12A MIPI Analog DPHY driver"
48 Enable this to support the Meson MIPI Analog DPHY found in Meson G12A
98 tristate "Meson AXG MIPI DPHY driver"
105 Enable this to support the Meson MIPI DPHY found in Meson AXG
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-csidphy.c3 * Rockchip MIPI RX Innosilicon DPHY driver
17 #include <linux/phy/phy-mipi-dphy.h>
275 /* Reset dphy analog part */ in rockchip_inno_csidphy_power_on()
281 /* Reset dphy digital part */ in rockchip_inno_csidphy_power_on()
419 .compatible = "rockchip,px30-csi-dphy",
423 .compatible = "rockchip,rk1808-csi-dphy",
427 .compatible = "rockchip,rk3326-csi-dphy",
431 .compatible = "rockchip,rk3368-csi-dphy",
435 .compatible = "rockchip,rk3568-csi-dphy",
439 .compatible = "rockchip,rk3588-csi-dphy",
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H A Dphy-rockchip-dphy-rx0.c3 * Rockchip MIPI Synopsys DPHY RX0 driver
25 #include <linux/phy/phy-mipi-dphy.h>
64 "dphy-ref",
65 "dphy-cfg",
200 /* dphy start */ in rk_dphy_enable()
316 .compatible = "rockchip,rk3399-mipi-dphy-rx0",
375 .name = "rockchip-mipi-dphy-rx0",
382 MODULE_DESCRIPTION("Rockchip MIPI Synopsys DPHY RX0 driver");
/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-csi-0-5.c34 DPHY = 0, enumerator
79 * The driver currently supports DPHY and CD-PHY phys, in mtk_mipi_phy_power_on()
80 * but the only mode supported is DPHY, in mtk_mipi_phy_power_on()
81 * so CD-PHY capable phys must be configured in DPHY mode in mtk_mipi_phy_power_on()
183 priv->mode = DPHY; in mtk_mipi_cdphy_xlate()
198 priv->mode = DPHY; in mtk_mipi_cdphy_xlate()
248 port->type = DPHY; in mtk_mipi_cdphy_probe()
/linux/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.h1100 #define DSI_PHY_CTRL_3 0x08C /* DPHY Control Register 3 */
1108 #define DSI_PHY_RCOMP_0 0x0B0 /* DPHY Rcomp Control Register */
1111 #define DSI_PHY_TIME_0 0x0C0 /* DPHY Timing Control Register 0 */
1112 #define DSI_PHY_TIME_1 0x0C4 /* DPHY Timing Control Register 1 */
1113 #define DSI_PHY_TIME_2 0x0C8 /* DPHY Timing Control Register 2 */
1114 #define DSI_PHY_TIME_3 0x0CC /* DPHY Timing Control Register 3 */
1115 #define DSI_PHY_TIME_4 0x0D0 /* DPHY Timing Control Register 4 */
1116 #define DSI_PHY_TIME_5 0x0D4 /* DPHY Timing Control Register 5 */
1208 /* DSI_PHY_CTRL_2 0x0088 DPHY Control Register 2 */
1210 /* DPHY LP Receiver Enable */
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c35 /* DPHY registers */
91 bool is_combo; /* MIPI DPHY and LVDS PHY combo */
109 /* DPHY PLL parameters */
113 /* DPHY register values */
139 .name = "mipi-dphy",
149 dev_err(&phy->dev, "Failed to write DPHY reg %d: %d\n", reg, in phy_write()
531 dev_err(&phy->dev, "Could not get DPHY lock (%d)!\n", ret); in mixel_dphy_power_on_mipi_dphy()
620 dev_err(&phy->dev, "Failed to set PHY mode to MIPI DPHY\n"); in mixel_dphy_set_mode()
652 { .compatible = "fsl,imx8mq-mipi-dphy",
654 { .compatible = "fsl,imx8qxp-mipi-dphy",
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/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml207 mipi-dphy-rx0:
210 $ref: /schemas/phy/rockchip-mipi-dphy-rx0.yaml#
332 mipi_dphy_rx0: mipi-dphy-rx0 {
333 compatible = "rockchip,rk3399-mipi-dphy-rx0";
337 clock-names = "dphy-ref", "dphy-cfg", "grf";

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