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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dcdns,dphy-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence DPHY Rx
10 - Pratyush Yadav <pratyush@kernel.org>
15 - const: cdns,dphy-rx
20 "#phy-cells":
23 power-domains:
27 - compatible
[all …]
H A Dallwinner,sun6i-a31-mipi-dphy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI D-PHY Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - const: allwinner,sun50i-a100-mipi-dphy
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dnxp,imx8mq-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
20 - fsl,imx8mq-mipi-csi2
27 - description: core is the RX Controller Core Clock input. This clock
[all …]
H A Dcdns,csi2rx.txt1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18 - phys: phandle to the external D-PHY, phy-names must be provided
19 - phy-names: must contain "dphy", if the implementation uses an
20 external D-PHY
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/freebsd/sys/contrib/device-tree/src/riscv/allwinner/
H A Dsunxi-d1s-t113.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
4 #include <dt-bindings/clock/sun6i-rtc.h>
5 #include <dt-bindings/clock/sun8i-de2.h>
6 #include <dt-bindings/clock/sun8i-tcon-top.h>
7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sun8i-de2.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
[all …]
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun8i-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp-table-cpu {
50 compatible = "operating-points-v2";
51 opp-shared;
53 opp-120000000 {
54 opp-hz = /bits/ 64 <120000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk356x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
H A Dpx30.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-binding
[all...]
H A Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
[all …]
H A Dimx8mq-evk.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 /dts-v1/;
13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
16 stdout-path = &uart1;
24 pcie0_refclk: pcie0-refclk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <100000000>;
30 reg_pcie1: regulator-pcie {
[all …]
H A Dimx8mq-librem5-devkit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 Purism SPC
6 /dts-v1/;
8 #include "dt-bindings/input/input.h"
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include "dt-bindings/pwm/pwm.h"
12 #include "dt-bindings/usb/pd.h"
17 compatible = "purism,librem5-devkit", "fsl,imx8mq";
19 backlight_dsi: backlight-dsi {
[all …]
/freebsd/sys/dev/axgbe/
H A Dxgbe-phy-v1.c116 #include "xgbe-common.h"
151 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_an_outcome()
155 XGBE_SET_LP_ADV(&pdata->phy, Autoneg); in xgbe_phy_an_outcome()
156 XGBE_SET_LP_ADV(&pdata->phy, Backplane); in xgbe_phy_an_outcome()
162 XGBE_SET_LP_ADV(&pdata->phy, Pause); in xgbe_phy_an_outcome()
164 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause); in xgbe_phy_an_outcome()
167 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg); in xgbe_phy_an_outcome()
169 if (pdata->phy.pause_autoneg) { in xgbe_phy_an_outcome()
170 /* Set flow control based on auto-negotiation result */ in xgbe_phy_an_outcome()
171 pdata->phy.tx_pause = 0; in xgbe_phy_an_outcome()
[all …]
H A Dxgbe-phy-v2.c116 #include "xgbe-common.h"
142 /* Rate-change complete wait/retry count */
275 * Optical specification compliance - denotes wavelength
306 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
307 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
314 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
315 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
334 /* Re-driver related definitions */
407 /* Re-driver support */
429 return (pdata->i2c_if.i2c_xfer(pdata, i2c_op)); in xgbe_phy_i2c_xfer()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
25 compatible = "mmio-sram";
[all …]
H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
25 #address-cells = <2>;
26 #size-cells = <2>;
28 #interrupt-cells = <3>;
[all …]
H A Dk3-am62p-j722s-common-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 gic500: interrupt-controller@1800000 {
16 compatible = "arm,gic-v3";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 #interrupt-cells = <3>;
[all …]
H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
[all …]
H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
[all …]
H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-g12-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h>
13 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]

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