| /freebsd/sys/contrib/device-tree/Bindings/display/exynos/ |
| H A D | exynos_dp.txt | 5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
11 Base address of DP PHY register.
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
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| /freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
| H A D | dp-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MSM Display Port Controller
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
13 Device tree bindings for DisplayPort host controller for MSM targets
19 - enum:
20 - qcom,sc7180-dp
21 - qcom,sc7280-dp
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| H A D | qcom,x1e80100-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abel.vesa@linaro.org>
13 X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces, etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,x1e80100-mdss
24 - description: Display AHB
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| H A D | qcom,sc7180-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mds
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| H A D | dpu-sc7180.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
20 - const: qcom,sc7180-mdss
25 reg-names:
28 power-domains:
33 - description: Display AHB clock from gcc
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| H A D | qcom,sc7280-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mds
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | analogix_dp.txt | 3 Required properties for dp-controller:
4 -compatible:
6 * "samsung,exynos5-dp"
7 * "rockchip,rk3288-dp"
8 * "rockchip,rk3399-edp"
9 -reg:
10 physical base address of the controller and length
12 -interrupts:
14 -clocks:
15 from common clock binding: handle to dp clock.
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | exynos5260-clock.txt | 1 * Samsung Exynos5260 Clock Controller
4 independently from the device-tree. These clock controllers
11 dt-bindings/clock/exynos5260-clk.h header and can be used in
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
21 - "xrtcxti" - input clock from XRTCXTI
22 - "ioclk_pcm_extclk" - pcm external operation clock
23 - "ioclk_spdif_extclk" - spdif external operation clock
24 - "ioclk_i2s_cdclk" - i2s0 codec clock
29 These clocks are fed into the clock controller and then routed to
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| H A D | qcom,sm8450-dispcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8450
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
16 See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
21 - qcom,sm8450-dispcc
26 - description: Board XO source
27 - description: Board Always On XO source
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| H A D | qcom,sm8550-dispcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8550
10 - Bjorn Andersson <andersson@kernel.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
18 - include/dt-bindings/clock/qcom,sm8550-dispcc.h
19 - include/dt-bindings/clock/qcom,sm8650-dispcc.h
20 - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
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| /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/ |
| H A D | mediatek,dp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dp
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| /freebsd/sys/contrib/device-tree/Bindings/soc/samsung/ |
| H A D | exynos-pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
18 - googl
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| /freebsd/sys/contrib/device-tree/Bindings/display/rockchip/ |
| H A D | rockchip,analogix-dp.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - rockchip,rk3288-dp
17 - rockchip,rk3399-edp
23 clock-names:
26 - const: dp
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| H A D | analogix_dp-rockchip.txt | 5 - compatible: "rockchip,rk3288-dp",
6 "rockchip,rk3399-edp";
8 - reg: physical base address of the controller and length
10 - clocks: from common clock binding: handle to dp clock.
13 - clock-names: from common clock binding:
14 Required elements: "dp" "pclk"
16 - resets: Must contain an entry for each entry in reset-names.
19 - pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
20 - pinctrl-0: pin-control mode. should be <&edp_hpd>
22 - reset-names: Must include the name "dp"
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| /freebsd/sys/dev/ida/ |
| H A D | ida_disk.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
83 * to complete. Multi-page transfers are supported. All I/O requests must
91 drv = bp->bio_disk->d_drv1; in idad_strategy()
93 bp->bio_error = EINVAL; in idad_strategy()
100 if (drv->flags & DRV_WRITEPROT && (bp->bio_cmd == BIO_WRITE)) { in idad_strategy()
101 bp->bio_error = EROFS; in idad_strategy()
105 if ((bp->bio_cmd != BIO_READ) && (bp->bio_cmd != BIO_WRITE)) { in idad_strategy()
106 bp->bio_error = EOPNOTSUPP; in idad_strategy()
110 bp->bio_driver1 = drv; in idad_strategy()
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | qcom,sc8280xp-qmp-usb43dp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43d
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| H A D | qcom,sc7180-qmp-usb3-dp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm QMP USB3 DP PHY controller (SC7180)
11 The QMP PHY controller supports physical layer functionality for a number of
15 qcom,sc8280xp-qmp-usb43dp-phy.yaml.
18 - Wesley Cheng <quic_wcheng@quicinc.com>
23 - enum:
24 - qcom,sc7180-qmp-usb3-dp-phy
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| /freebsd/sys/dev/mfi/ |
| H A D | mfi_disk.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
104 sc->ld_dev = dev; in mfi_disk_attach()
105 sc->ld_id = ld_info->ld_config.properties.ld.v.target_id; in mfi_disk_attach()
106 sc->ld_unit = device_get_unit(dev); in mfi_disk_attach()
107 sc->ld_info = ld_info; in mfi_disk_attach()
108 sc->ld_controller = device_get_softc(device_get_parent(dev)); in mfi_disk_attach()
109 sc->ld_flags = 0; in mfi_disk_attach()
111 sectors = ld_info->size; in mfi_disk_attach()
113 mtx_lock(&sc->ld_controller->mfi_io_lock); in mfi_disk_attach()
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| H A D | mfi_syspd.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
8 * Copyright 1994-2009 The FreeBSD Project.
106 sc->pd_dev = dev; in mfi_syspd_attach()
107 sc->pd_id = pd_info->ref.v.device_id; in mfi_syspd_attach()
108 sc->pd_unit = device_get_unit(dev); in mfi_syspd_attach()
109 sc->pd_info = pd_info; in mfi_syspd_attach()
110 sc->pd_controller = device_get_softc(device_get_parent(dev)); in mfi_syspd_attach()
111 sc->pd_flags = 0; in mfi_syspd_attach()
113 sectors = pd_info->raw_size; in mfi_syspd_attach()
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| /freebsd/sys/contrib/device-tree/Bindings/display/samsung/ |
| H A D | samsung,exynos5-dp.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
17 const: samsung,exynos5-dp
25 clock-names:
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| /freebsd/sys/contrib/device-tree/Bindings/display/tegra/ |
| H A D | nvidia,tegra124-sor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-so
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | dp-aux-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 are hooked up to them. This is the DP AUX bus. Over the DP AUX bus
16 particular, DP sinks support DDC over DP AUX which allows tunneling
19 To model this relationship, DP sinks should be placed as children
20 of the DP controller under the "aux-bus" node.
23 possible it will be extended in the future to handle the DP case.
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| /freebsd/sys/contrib/device-tree/Bindings/display/connector/ |
| H A D | dp-connector.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/connector/dp-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomi Valkeinen <tomi.valkeinen@ti.com>
14 const: dp-connector
20 - full-size
21 - mini
23 hpd-gpios:
27 dp-pwr-supply:
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| /freebsd/sys/dev/aac/ |
| H A D | aac_disk.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
92 aac_disk_open(struct disk *dp) in aac_disk_open() argument
98 sc = (struct aac_disk *)dp->d_drv1; in aac_disk_open()
105 /* check that the controller is up and running */ in aac_disk_open()
106 if (sc->ad_controller->aac_state & AAC_STATE_SUSPEND) { in aac_disk_open()
107 device_printf(sc->ad_controller->aac_dev, in aac_disk_open()
108 "Controller Suspended controller state = 0x%x\n", in aac_disk_open()
109 sc->ad_controller->aac_state); in aac_disk_open()
113 sc->ad_flags |= AAC_DISK_OPEN; in aac_disk_open()
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| /freebsd/share/man/man4/ |
| H A D | bce.4 | 1 .\" Copyright (c) 2006-2014 QLogic Corporation
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
55 same controller.
62 .Bl -item -offset indent -compact
72 10/100/1000Mbps operation in full-duplex mode
74 10/100Mbps operation in half-duplex mode
80 .Bl -tag -width ".Cm 10baseT/UTP"
92 .Cm full-duplex
94 .Cm half-duplex
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