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/linux/Documentation/devicetree/bindings/regulator/
H A Ddlg,da9121.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adam Ward <Adam.Ward.opensource@diasemi.com>
13 Dialog Semiconductor DA9121 Single-channel 10A double-phase buck converter
14 Dialog Semiconductor DA9122 Double-channel 5A single-phase buck converter
15 Dialog Semiconductor DA9220 Double-channel 3A single-phase buck converter
16 Dialog Semiconductor DA9217 Single-channel 6A double-phase buck converter
17 Dialog Semiconductor DA9130 Single-channel 10A double-phase buck converter
18 Dialog Semiconductor DA9131 Double-channel 5A single-phase buck converter
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/linux/fs/bcachefs/
H A Dbtree_gc.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * Note that some references will have the same GC position as others - e.g.
23 * without that, we would at best double count sometimes.
25 * That part is important - whenever calling bch2_mark_pointers(), a lock _must_
33 /* Position of (the start of) a gc phase: */
34 static inline struct gc_pos gc_phase(enum gc_phase phase) in gc_phase() argument
36 return (struct gc_pos) { .phase = phase, }; in gc_phase()
43 .phase = GC_PHASE_btree, in gc_pos_btree()
53 return -2; in gc_btree_order()
55 return -1; in gc_btree_order()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c2 * Copyright 2020-2021 Advanced Micro Devices, Inc.
37 optc1->tg_regs->reg
40 optc1->base.ctx
44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
182 double vtotal_avg) in optc3_fpu_set_vrr_m_const()
185 double vtotal_min, vtotal_max; in optc3_fpu_set_vrr_m_const()
186 double ratio, modulo, phase; in optc3_fpu_set_vrr_m_const() local
193 * VOTAL_MAX - VTOTAL_MIN = 1 in optc3_fpu_set_vrr_m_const()
201 * of lines in a frame - 1'. in optc3_fpu_set_vrr_m_const()
213 optc->funcs->set_vtotal_min_max(optc, 0, 0); in optc3_fpu_set_vrr_m_const()
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/linux/drivers/ptp/
H A Dptp_idt82p33.h1 /* SPDX-License-Identifier: GPL-2.0+ */
46 * @brief Maximum absolute value for write phase offset in nanoseconds
50 /** @brief Phase offset resolution
52 * DPLL phase offset = 10^15 fs / ( System Clock * 2^13)
64 /* Workaround for TOD-to-output alignment issue */
67 /* double dco mode */
/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,rz-mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This hardware block consists of eight 16-bit timer channels and one
14 32-bit timer channel. It supports the following specifications:
15 - Pulse input/output: 28 lines max
16 - Pulse input 3 lines
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/linux/drivers/block/
H A Dswim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * 2004-08-21 (lv) - Initial implementation
12 * 2008-10-30 (lv) - Port to 2.6
18 #include <linux/blk-mq.h>
39 #define DRIVER_VERSION "Version 0.2 (2008-10-30)"
41 #define REG(x) unsigned char x, x ## _pad[0x200 - 1];
63 #define swim_write(base, reg, v) out_8(&(base)->write_##reg, (v))
64 #define swim_read(base, reg) in_8(&(base)->read_##reg)
87 #define iwm_write(base, reg, v) out_8(&(base)->reg, (v))
88 #define iwm_read(base, reg) in_8(&(base)->reg)
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/linux/drivers/mmc/host/
H A Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
46 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_get_internal_phase()
51 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_internal_phase()
78 struct dw_mci_rockchip_priv_data *priv = host->priv; in rockchip_mmc_get_phase()
79 struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; in rockchip_mmc_get_phase()
81 if (priv->internal_phase) in rockchip_mmc_get_phase()
89 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_set_internal_phase()
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H A Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
123 #define INVALID_TUNING_PHASE -1
140 /* Max load for eMMC Vdd-io supply */
146 /* Max load for SD Vdd-io supply */
150 msm_host->var_ops->msm_readl_relaxed(host, offset)
153 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
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/linux/tools/mm/
H A Dthp_swap_allocator_test.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * can be enabled by "-s".
15 * echo never > /sys/kernel/mm/transparent_hugepage/hugepages-2048kB/enabled
16 * echo always > /sys/kernel/mm/transparent_hugepage/hugepages-64kB/enabled
20 * w/o "-s".
22 * Author(s): Barry Song <v-songbaohua@oppo.com>
44 "/sys/kernel/mm/transparent_hugepage/hugepages-64kB/stats/swpout"
46 "/sys/kernel/mm/transparent_hugepage/hugepages-64kB/stats/swpout_fallback"
63 * currently don't support large folios swap-in.
126 if (strcmp(argv[i], "-s") == 0) in main()
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/linux/arch/parisc/math-emu/
H A Dfmpyfadd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
15 * Double Floating-point Multiply Fused Add
16 * Double Floating-point Multiply Negate Fused Add
17 * Single Floating-point Multiply Fused Add
18 * Single Floating-point Multiply Negate Fused Add
41 * Double Floating-point Multiply Fused Add
77 mpy_exponent = Dbl_exponent(opnd1p1) + Dbl_exponent(opnd2p1) - DBL_BIAS; in dbl_fmpyfadd()
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H A Ddfsub.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
15 * Double_subtract: subtract two double precision values.
33 * Double_subtract: subtract two double precision values.
266 diff_exponent = result_exponent - right_exponent; in dbl_fsub()
289 * normalization phase. in dbl_fsub()
313 /* Must have been "x-x" or "x+(-x)". */ in dbl_fsub()
319 result_exponent--; in dbl_fsub()
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H A Ddfadd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
15 * Double_add: add two double precision values.
33 * Double_add: add two double precision values.
263 diff_exponent = result_exponent - right_exponent; in dbl_fadd()
286 * normalization phase. in dbl_fadd()
310 /* Must have been "x-x" or "x+(-x)". */ in dbl_fadd()
316 result_exponent--; in dbl_fadd()
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/linux/drivers/mtd/spi-nor/
H A Dsfdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i) ((i) - 1)
57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
59 * instruction phase.
60 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
63 * Writing only one byte to the status register has the side-effect of
67 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
70 * - 011b: QE is bit 7 of status register 2. It is set via Write status
74 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
79 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn401/
H A Ddcn401_fpu.c1 // SPDX-License-Identifier: MIT
16 double pstate_latency_us = clk_mgr->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn401_build_wm_range_table_fpu()
17 double fclk_change_latency_us = clk_mgr->ctx->dc->dml.soc.fclk_change_latency_us; in dcn401_build_wm_range_table_fpu()
18 double sr_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_exit_time_us; in dcn401_build_wm_range_table_fpu()
19 double sr_enter_plus_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn401_build_wm_range_table_fpu()
21 uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; in dcn401_build_wm_range_table_fpu()
22 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
24 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
30 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_secon… in dcn401_build_wm_range_table_fpu()
32 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->bw_params->clk_… in dcn401_build_wm_range_table_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_dpia.c44 link->ctx->logger
66 DPIA_TS_UFP_DONE = 0xff /* Done training DPTX-to-DPIA hop. */
95 * @param[out] lt_settings Link settings and drive settings (voltage swing and pre-emphasis).
106 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", in dpia_configure_link()
108 link->link_id.enum_id - ENUM_ID_1, in dpia_configure_link()
109 lt_settings->lttpr_mode); in dpia_configure_link()
116 dp_get_lttpr_mode_override(link, &lt_settings->lttpr_mode); in dpia_configure_link()
119 if (status != DC_OK && link->is_hpd_pending) in dpia_configure_link()
124 if (status != DC_OK && link->is_hpd_pending) in dpia_configure_link()
129 if (status != DC_OK && link->is_hpd_pending) in dpia_configure_link()
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/linux/tools/perf/Documentation/
H A Dperf-c2c.txt1 perf-c2c(1)
5 ----
6 perf-c2c - Shared Data C2C/HITM Analyzer.
9 --------
12 'perf c2c record' [<options>] \-- [<record command options>] <command>
16 -----------
27 required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the
32 - memory address of the access
33 - type of the access (load and store details)
34 - latency (in cycles) of the load access
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/linux/drivers/scsi/
H A Dmesh.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
85 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id))
96 u8 phase; member
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/linux/tools/testing/selftests/net/
H A Dsrv6_end_next_csid_l3vpn_test.sh2 # SPDX-License-Identifier: GPL-2.0
6 # This script is designed for testing the support of NEXT-C-SID flavor for SRv6
12 # two hosts and four routers. Hosts hs-1 and hs-2 are connected through an
13 # IPv4/IPv6 L3 VPN service, offered by routers rt-1, rt-2, rt-3 and rt-4 using
14 # the NEXT-C-SID flavor. The key components for such VPNs are:
22 # iii) The NEXT-C-SID mechanism [2] offers the possibility of encoding several
23 # SRv6 segments within a single 128-bit SID address, referred to as a
24 # Compressed SID (C-SID) container. In this way, the length of the SID
26 # The NEXT-C-SID is provided as a "flavor" of the SRv6 End behavior
27 # which advances the current C-SID (i.e. the Locator-Node Function defined
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H A Dsrv6_end_x_next_csid_l3vpn_test.sh2 # SPDX-License-Identifier: GPL-2.0
7 # This script is designed for testing the support of NEXT-C-SID flavor for SRv6
13 # two hosts and four routers. Hosts hs-1 and hs-2 are connected through an
14 # IPv4/IPv6 L3 VPN service, offered by routers rt-1, rt-2, rt-3 and rt-4 using
15 # the NEXT-C-SID flavor. The key components for such VPNs are:
24 # iii) The NEXT-C-SID mechanism [2] offers the possibility of encoding several
25 # SRv6 segments within a single 128-bit SID address, referred to as a
26 # Compressed SID (C-SID) container. In this way, the length of the SID
28 # The NEXT-C-SID is provided as a "flavor" of the SRv6 End.X behavior
29 # which advances the current C-SID (i.e. the Locator-Node Function defined
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/linux/Documentation/sound/cards/
H A Dcmipci.rst2 Brief Notes on C-Media 8338/8738/8768/8770 Driver
8 Front/Rear Multi-channel Playback
9 ---------------------------------
13 DACs, both streams are handled independently unlike the 4/6ch multi-
22 - The first DAC supports U8 and S16LE formats, while the second DAC
24 - The second DAC supports only two channel stereo.
44 on and "double DAC" mode. Actually I could hear separate 4 channels
51 control switch in the driver "Line-In As Rear", which you can change
52 via alsamixer or somewhat else. When this switch is on, line-in jack
60 4/6 Multi-Channel Playback
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/linux/Documentation/admin-guide/media/
H A Dphilips.rst1 .. SPDX-License-Identifier: GPL-2.0
7 E-mail: webcam@smcc.demon.nl Last updated: 2004-01-19
30 * Samsung MPC-C10
31 * Samsung MPC-C30
33 * AME CU-001
34 * Visionite VCS-UM100
35 * Visionite VCS-UC300
46 the latter, since it makes troubleshooting a lot easier. The built-in
50 camera; some programs depend on a particular image-size or -format and
60 Specifies the desired framerate. Is an integer in the range of 4-30.
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/linux/Documentation/RCU/Design/Memory-Ordering/
H A DTree-RCU-Memory-Ordering.rst2 A Tour Through TREE_RCU's Grace-Period Memory Ordering
13 grace-period memory ordering guarantee is provided.
18 RCU grace periods provide extremely strong memory-ordering guarantees
19 for non-idle non-offline code.
22 period that are within RCU read-side critical sections.
25 of that grace period that are within RCU read-side critical sections.
27 Note well that RCU-sched read-side critical sections include any region
30 an extremely small region of preemption-disabled code, one can think of
36 In the most common use case, phase one removes an element from
37 a linked RCU-protected data structure, and phase two frees that element.
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/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
200 "BriefDescription": "Read-write data cache collisions"
210 …phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtrac…
280 …double-word boundary, which causes it to require an additional slice than than what normally would…
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
395 …double-word boundary, which causes it to require an additional slice than than what normally would…
430 "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
450 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
455 "BriefDescription": "D-side L2 MRU touch commands sent to the L2"
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/linux/drivers/net/wan/
H A Dfarsync.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
23 * used with the FarSite T-Series cards (T2P & T4P) running in the high
30 * purpose (FarSite T-series).
117 unsigned char structure; /* unframed, double, crc4, f4, f12, */
121 unsigned char lineBuildOut; /* 0, -7.5, -15, -22 */
158 #define FSTVAL_PHASE 0x00000800 /* Clock phase */
/linux/drivers/gpu/drm/vc4/
H A Dvc4_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
276 return state->fb && !WARN_ON(!state->crtc); in plane_enabled()
281 struct vc4_dev *vc4 = to_vc4_dev(plane->dev); in vc4_plane_duplicate_state()
282 struct vc4_hvs *hvs = vc4->hvs; in vc4_plane_duplicate_state()
286 if (WARN_ON(!plane->state)) in vc4_plane_duplicate_state()
289 vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL); in vc4_plane_duplicate_state()
293 memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm)); in vc4_plane_duplicate_state()
296 if (vc4_state->upm_handle[i]) in vc4_plane_duplicate_state()
297 refcount_inc(&hvs->upm_refcounts[vc4_state->upm_handle[i]].refcount); in vc4_plane_duplicate_state()
300 vc4_state->dlist_initialized = 0; in vc4_plane_duplicate_state()
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