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Searched +full:dma +full:- +full:ring +full:- +full:reset +full:- +full:quirk (Results 1 – 11 of 11) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dk3-ringacc.txt1 * Texas Instruments K3 NavigatorSS Ring Accelerator
3 The Ring Accelerator (RA) is a machine which converts read/write accesses
5 circular data structure in memory. The RA eliminates the need for each DMA
6 controller which needs to access ring elements from having to know the current
7 state of the ring (base address, current offset). The DMA controller
10 with a new address which corresponds to the head or tail element of the ring
13 The Ring Accelerator is a hardware module that is responsible for accelerating
17 - compatible : Must be "ti,am654-navss-ringacc";
18 - reg : Should contain register location and length of the following
20 - reg-names : should be
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
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H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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H A Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
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H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm8550.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
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/freebsd/sys/dev/usb/controller/
H A Dehci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
35 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
37 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
154 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, in ehci_iterate_hw_softc()
157 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, in ehci_iterate_hw_softc()
160 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, in ehci_iterate_hw_softc()
164 cb(bus, sc->sc_hw.intr_start_pc + i, in ehci_iterate_hw_softc()
165 sc->sc_hw.intr_start_pg + i, in ehci_iterate_hw_softc()
170 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, in ehci_iterate_hw_softc()
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/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_reset.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
78 #define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)] in write_common()
82 for (r = 0; r < ia->rows; r++) { in write_common()
85 /* On channel change, don't reset the PCU registers */ in write_common()
109 * Places the device in and out of reset and then places sane
113 * bChannelChange is used to preserve DMA/PCU registers across
114 * a HW Reset during channel change.
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/freebsd/sys/dev/bwn/
H A Dif_bwn.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
123 "uses DMA");
514 /* Host bridge cores for which D11 quirk flags should be applied */
544 sc->sc_dev = dev; in bwn_attach()
546 sc->sc_debug = bwn_debug; in bwn_attach()
553 sc->sc_quirks = bhnd_device_quirks(dev, bwn_devices, in bwn_attach()
558 sc->sc_quirks |= bhnd_device_quirks(hostb, bridge_devices, in bwn_attach()
562 /* DMA explicitly disabled? */ in bwn_attach()
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/freebsd/sys/dev/pci/
H A Dpci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
101 static int pci_has_quirk(uint32_t devid, int quirk);
237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
256 * or the CMIC-SL (AKA ServerWorks GC_LE).
274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
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