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/linux/arch/arm/boot/dts/st/
H A Dste-dbx5x0.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/ste-db8500-clkout.h>
9 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
10 #include <dt-bindings/mfd/dbx500-prcmu.h>
11 #include <dt-bindings/arm/ux500_pm_domains.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/thermal/thermal.h>
16 #address-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped registers. channels are split into two groups, called
12 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
[all …]
H A Drenesas,rz-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ DMA Controller
10 - Biju Das <biju.das.jz@bp.renesas.com>
15 - items:
16 - enum:
17 - renesas,r7s72100-dmac # RZ/A1H
18 - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
[all …]
H A Dti-edma.txt4 Controller(s) (TC). The CC is the main entry for DMA users since it is
5 responsible for the DMA channel handling, while the TCs are responsible to
6 execute the actual DMA tansfer.
8 ------------------------------------------------------------------------------
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
20 - reg: Memory map of eDMA CC
[all …]
H A Dnvidia,tegra210-adma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/nvidia,tegra210-adma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Audio DMA (ADMA) controller
10 The Tegra Audio DMA controller is used for transferring data
14 - Jon Hunter <jonathanh@nvidia.com>
19 - enum:
20 - nvidia,tegra210-adma
21 - nvidia,tegra186-adma
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsam9x60.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/mfd/at91-usart.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
19 #address-cells = <1>;
[all …]
H A Dsama7g5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/dma/at91.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/mfd/at91-usart.h>
19 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
[all …]
H A Dsama5d2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
9 #include <dt-bindings/dma/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
13 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 interrupt-parent = <&aic>;
[all …]
H A Dlan966x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h616.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h616-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/clock/sun6i-rtc.h>
10 #include <dt-bindings/reset/sun50i-h616-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
H A Dsun50i-a100.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/clock/sun6i-rtc.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
[all …]
H A Dsunxi-h3-h5.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun6i-rtc.h>
44 #include <dt-bindings/clock/sun8i-de2.h>
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/reset/sun8i-de2.h>
49 #include <dt-bindings/reset/sun8i-h3-ccu.h>
50 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 interrupt-parent = <&gic>;
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dam33xx-usb.txt3 - compatible: ti,am33xx-usb
4 - reg: offset and length of the usbss register sets
5 - ti,hwmods : must be "usb_otg_hs"
9 node and its PHY node are optional. The DMA node is also optional.
13 - compatible: ti,am335x-usb-ctrl-module
14 - reg: offset and length of the "USB control registers" in the "Control
17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
22 compatible: ti,am335x-usb-phy
25 reg-names: phy
31 - compatible: ti,musb-am33xx
[all …]
H A Dda8xx-usb.txt3 For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms.
7 - compatible : Should be set to "ti,da830-musb".
9 - reg: Offset and length of the USB controller register set.
11 - interrupts: The USB interrupt number.
13 - interrupt-names: Should be set to "mc".
15 - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg".
17 - phys: Phandle for the PHY device
19 - phy-names: Should be "usb-phy"
21 - dmas: specifies the dma channels
23 - dma-names: specifies the names of the channels. Use "rxN" for receive
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dingenic,mmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: mmc-controller.yaml#
18 - enum:
19 - ingenic,jz4740-mmc
20 - ingenic,jz4725b-mmc
21 - ingenic,jz4760-mmc
22 - ingenic,jz4775-mmc
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
[all …]
H A Dr8a7793.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M2-N (R8A77930) SoC
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/r8a7793-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
37 compatible = "fixed-clock";
[all …]
H A Dr8a7794.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car E2 (R8A77940) SoC
9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7794-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dkeystone-navigator-dma.txt1 Keystone Navigator DMA Controller
3 This document explains the device tree bindings for the packet dma
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
8 CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
13 ------------------
15 ------------------
17 |-> DMA instance #0
19 |-> DMA instance #1
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dadi,axi-spdif-tx.txt1 ADI AXI-SPDIF controller
4 - compatible : Must be "adi,axi-spdif-tx-1.00.a"
5 - reg : Must contain SPDIF core's registers location and length
6 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
9 - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
11 - dmas: Pairs of phandle and specifier for the DMA channel that is used by
12 the core. The core expects one dma channel for transmit.
13 - dma-names : Must be "tx"
15 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
17 * resource-names.txt
[all …]
H A Dallwinner,sun4i-a10-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#sound-dai-cells":
19 - const: allwinner,sun4i-a10-i2s
20 - const: allwinner,sun6i-a31-i2s
21 - const: allwinner,sun8i-a83t-i2s
[all …]
/linux/Documentation/devicetree/bindings/gpu/host1x/
H A Dnvidia,tegra210-nvenc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dqcom,bam-dmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,bam-dmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
15 or MSM8974. It is built using a simple protocol layer on top of a DMA engine
16 (Qualcomm BAM DMA) and bidirectional interrupts to coordinate power control.
20 DMA engine). As such it is specific to a firmware version, not a particular
25 const: qcom,bam-dmux
32 - description: Power control
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dmicrochip,spi-pic32.txt4 - compatible: Should be "microchip,pic32mzda-spi".
5 - reg: Address and length of register space for the device.
6 - interrupts: Should contain all three spi interrupts in sequence
7 of <fault-irq>, <receive-irq>, <transmit-irq>.
8 - interrupt-names: Should be "fault", "rx", "tx" in order.
9 - clocks: Phandle of the clock generating SPI clock on the bus.
10 - clock-names: Should be "mck0".
11 - cs-gpios: Specifies the gpio pins to be used for chipselects.
12 See: Documentation/devicetree/bindings/spi/spi-bus.txt
15 - dmas: Two or more DMA channel specifiers following the convention outlined
[all …]

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