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/linux/Documentation/devicetree/bindings/crypto/
H A Dst,stm32-hash.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/st,stm32-hash.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Lionel Debieve <lionel.debieve@foss.st.com>
19 - st,stn8820-hash
20 - stericsson,ux500-hash
21 - st,stm32f456-hash
22 - st,stm32f756-hash
23 - st,stm32mp13-hash
[all …]
/linux/drivers/dma/
H A Dloongson2-apb-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for the Loongson-2 APB DMA Controller
5 * Copyright (C) 2017-2023 Loongson Corporation
9 #include <linux/dma-mapping.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
21 #include "virt-dma.h"
32 #define LDMA_START BIT(3) /* DMA start operation */
33 #define LDMA_STOP BIT(4) /* DMA stop operation */
34 #define LDMA_CONFIG_MASK GENMASK_ULL(4, 0) /* DMA controller config bits mask */
41 #define LDMA_INT BIT(1) /* Enable DMA interrupts */
[all …]
H A Damba-pl08x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2010 ST-Ericsson SA
14 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
18 * has only two channels. So on these DMA controllers the number of channels
19 * and the number of incoming DMA signals are two totally different things.
27 * - CH_CONFIG register at different offset,
28 * - separate CH_CONTROL2 register for transfer size,
29 * - bigger maximum transfer size,
30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
31 * - no support for peripheral flow control.
[all …]
H A Dste_dma40.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Ericsson AB 2007-2008
4 * Copyright (C) ST-Ericsson SA 2008-2010
5 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
9 #include <linux/dma-mapping.h>
32 * struct stedma40_platform_data - Configuration struct for the dma device.
34 * @disabled_channels: A vector, ending with -1, that marks physical channels
45 * 0 means reading the number of channels from DMA HW but this is only valid
59 #define D40_PHY_CHAN -1
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/linux/sound/soc/pxa/
H A Dpxa2xx-ac97.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
15 #include <linux/dma/pxa-dma.h>
21 #include <sound/pxa2xx-lib.h>
24 #include <linux/platform_data/asoc-pxa.h>
28 #define MCDR 0x0060 /* Mic-in FIFO Data Register */
66 .maxburst = 32,
72 .maxburst = 32,
78 .maxburst = 16,
84 .maxburst = 16,
[all …]
H A Dpxa2xx-i2s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pxa2xx-i2s.c -- ALSA Soc Audio Layer
21 #include <sound/pxa2xx-lib.h>
24 #include <linux/platform_data/asoc-pxa.h>
26 #include "pxa2xx-i2s.h"
32 #define SACR1 (0x0004) /* Serial Audio I 2 S/MSB-Justified Control Register */
33 #define SASR0 (0x000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
39 #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
40 #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
84 .maxburst = 32,
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/linux/sound/soc/fsl/
H A Dfsl_asrc_dma.c1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale ASRC ALSA SoC Platform (DMA) driver
9 #include <linux/dma-mapping.h>
11 #include <linux/dma/imx-dma.h>
37 chan->private = param; in filter()
45 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_asrc_dma_complete()
46 struct fsl_asrc_pair *pair = runtime->private_data; in fsl_asrc_dma_complete()
48 pair->pos += snd_pcm_lib_period_bytes(substream); in fsl_asrc_dma_complete()
49 if (pair->pos >= snd_pcm_lib_buffer_bytes(substream)) in fsl_asrc_dma_complete()
50 pair->pos = 0; in fsl_asrc_dma_complete()
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H A Dimx-pcm-fiq.c1 // SPDX-License-Identifier: GPL-2.0+
2 // imx-pcm-fiq.c -- ALSA Soc Audio Layer
12 #include <linux/dma-mapping.h>
28 #include <linux/platform_data/asoc-imx-ssi.h>
30 #include "imx-ssi.h"
31 #include "imx-pcm.h"
48 struct snd_pcm_substream *substream = iprtd->substream; in snd_hrtimer_callback()
51 if (!atomic_read(&iprtd->playing) && !atomic_read(&iprtd->capturing)) in snd_hrtimer_callback()
56 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in snd_hrtimer_callback()
57 iprtd->offset = regs.ARM_r8 & 0xffff; in snd_hrtimer_callback()
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H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
66 * (bit-endianness must match byte-endianness). Processors typically write
68 * written in. So if the host CPU is big-endian, then only big-endian
91 * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS
[all …]
H A Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
58 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
65 if (sai->is_pdm_mode) { in fsl_sai_get_pins_state()
68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); in fsl_sai_get_pins_state()
72 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); in fsl_sai_get_pins_state()
76 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); in fsl_sai_get_pins_state()
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H A Dfsl_xcvr.c1 // SPDX-License-Identifier: GPL-2.0
19 #include "imx-pcm.h"
78 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
116 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_arc_mode_put()
117 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_arc_mode_put()
119 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_arc_mode_put()
130 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; in fsl_xcvr_arc_mode_get()
150 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_capds_bytes_info()
151 uinfo->count = FSL_XCVR_CAPDS_SIZE; in fsl_xcvr_type_capds_bytes_info()
162 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_get()
[all …]
H A Dfsl_aud2htx.c1 // SPDX-License-Identifier: GPL-2.0+
5 #include <linux/clk-provider.h>
18 #include <linux/dma-mapping.h>
21 #include "imx-pcm.h"
32 regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL, in fsl_aud2htx_trigger()
34 regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT, in fsl_aud2htx_trigger()
40 regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT, in fsl_aud2htx_trigger()
42 regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL, in fsl_aud2htx_trigger()
46 return -EINVAL; in fsl_aud2htx_trigger()
53 struct fsl_aud2htx *aud2htx = dev_get_drvdata(cpu_dai->dev); in fsl_aud2htx_dai_probe()
[all …]
/linux/include/sound/
H A Ddmaengine_pcm.h1 /* SPDX-License-Identifier: GPL-2.0+
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
15 * snd_pcm_substream_to_dma_direction - Get dma_transfer_direction for a PCM
19 * Return: DMA transfer direction
24 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in snd_pcm_substream_to_dma_direction()
50 * The DAI supports packed transfers, eg 2 16-bit samples in a 32-bit word.
52 * the supported sample formats and set the DMA transfe
77 u32 maxburst; global() member
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/linux/drivers/dma/dw/
H A Didma32.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2013,2018,2020-2021 Intel Corporation
38 struct device *slave = dwc->chan.slave; in idma32_get_slave_devfn()
43 return to_pci_dev(slave)->devfn; in idma32_get_slave_devfn()
48 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in idma32_initialize_chan_xbar()
54 /* DMA Channel ID Configuration register must be programmed first */ in idma32_initialize_chan_xbar()
58 value |= dwc->chan.chan_id; in idma32_initialize_chan_xbar()
63 value = readl(misc + DMA_CTL_CH(dwc->chan.chan_id)); in idma32_initialize_chan_xbar()
69 switch (dwc->direction) { in idma32_initialize_chan_xbar()
80 * Memory-to-Memory and Device-to-Device are ignored for now. in idma32_initialize_chan_xbar()
[all …]
/linux/sound/core/
H A Dpcm_dmaengine.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 * imx-pcm-dma-mx2.c, Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
8 * mxs-pcm.c, Copyright (C) 2011 Freescale Semiconductor, Inc.
9 * ep93xx-pcm.c, Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
32 return substream->runtime->private_data; in substream_to_prtd()
39 return prtd->dma_chan; in snd_dmaengine_pcm_get_chan()
44 * snd_hwparams_to_dma_slave_config - Convert hw_params to dma_slave_config
47 * @slave_config: DMA slave config
63 return -EINVAL; in snd_hwparams_to_dma_slave_config()
[all …]
/linux/sound/soc/atmel/
H A Dmchp-i2s-mcc.c1 // SPDX-License-Identifier: GPL-2.0
3 // Driver for Microchip I2S Multi-channel controller
29 * ---- I2S Controller Register map ----
75 * ---- Control Register (Write-only) ----
86 * ---- Mode Register A (Read/Write) ----
116 /* Transmitter uses one DMA channel ... */
123 /* Receiver uses one DMA channel ... */
135 /* Number of TDM Channels - 1 */
138 ((((ch) - 1) << 13) & MCHP_I2SMCC_MRA_NBCHAN_MASK)
169 * ---- Mode Register B (Read/Write) ----
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H A Dmchp-pdmc.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries
9 #include <dt-bindings/sound/microchip,pdmc.h>
24 * ---- PDMC Register map ----
37 * ---- Control Register (Write-only) ----
42 * ---- Mode Register (Read/Write) ----
66 * ---- Configuration Register (Read/Write) ----
75 * ---- Interrupt Enable/Disable/Mask/Status Registers ----
85 * ---- Version Register (Read-only) ----
94 * ---- DMA chunk size allowed ----
[all …]
H A Datmel-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
29 * ---- I2S Controller Register map ----
44 * ---- Control Register (Write-only) ----
55 * ---- Mode Register (Read/Write) ----
80 /* Receiver uses one DMA channel ... */
91 /* Transmitter uses one DMA channel ... */
124 * ---- Status Registers ----
143 * ---- Interrupt Enable/Disable/Mask Registers ----
215 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr); in atmel_i2s_interrupt()
216 regmap_read(dev->regmap, ATMEL_I2SC_IMR, &imr); in atmel_i2s_interrupt()
[all …]
/linux/arch/powerpc/platforms/512x/
H A Dmpc512x_lpbfifo.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2013-2015 Alexander Popov <alex.popov@linux.com>.
21 #include <linux/dma-direction.h>
22 #include <linux/dma-mapping.h>
55 * automatically disables LPBFIFO reading request to the DMA controller
61 * mpc512x_lpbfifo_irq - IRQ handler for LPB FIFO
76 if (!req || req->dir == MPC512X_LPBFIFO_REQ_DIR_READ) { in mpc512x_lpbfifo_irq()
81 status = in_be32(&lpbfifo.regs->status); in mpc512x_lpbfifo_irq()
83 dev_err(dev, "DMA transfer from RAM to peripheral failed\n"); in mpc512x_lpbfifo_irq()
84 out_be32(&lpbfifo.regs->enable, in mpc512x_lpbfifo_irq()
[all …]
/linux/drivers/crypto/
H A Datmel-aes.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
10 * Some ideas are from omap-aes.c driver.
30 #include <linux/dma-mapping.h>
41 #include "atmel-aes-regs.h"
42 #include "atmel-authenc.h"
253 snprintf(tmp, sz, "KEYWR[%u]", (offset - AES_KEYWR(0)) >> 2); in atmel_aes_reg_name()
260 snprintf(tmp, sz, "IDATAR[%u]", (offset - AES_IDATAR(0)) >> 2); in atmel_aes_reg_name()
267 snprintf(tmp, sz, "ODATAR[%u]", (offset - AES_ODATAR(0)) >> 2); in atmel_aes_reg_name()
274 snprintf(tmp, sz, "IVR[%u]", (offset - AES_IVR(0)) >> 2); in atmel_aes_reg_name()
[all …]
/linux/sound/soc/adi/
H A Daxi-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
63 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_trigger()
80 return -EINVAL; in axi_i2s_trigger()
83 regmap_update_bits(i2s->regmap, AXI_I2S_REG_CTRL, mask, val); in axi_i2s_trigger()
97 word_size = AXI_I2S_BITS_PER_FRAME / 2 - 1; in axi_i2s_hw_params()
98 bclk_div = DIV_ROUND_UP(clk_get_rate(i2s->clk_ref), bclk_rate) / 2 - 1; in axi_i2s_hw_params()
100 regmap_write(i2s->regmap, AXI_I2S_REG_CLK_CTRL, (word_size << 16) | in axi_i2s_hw_params()
113 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_startup()
[all …]
/linux/sound/soc/ti/
H A Domap-mcpdm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
5 * Copyright (C) 2009 - 2011 Texas Instruments
30 #include "omap-mcpdm.h"
31 #include "sdma-pcm.h"
64 * Stream DMA parameters
69 writel_relaxed(val, mcpdm->io_base + reg); in omap_mcpdm_write()
74 return readl_relaxed(mcpdm->io_base + reg); in omap_mcpdm_read()
80 dev_dbg(mcpdm->dev, "***********************\n"); in omap_mcpdm_reg_dump()
81 dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n", in omap_mcpdm_reg_dump()
[all …]
H A Domap-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-hdmi-audio.c -- OMAP4+ DSS HDMI audio support library
5 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
20 #include <sound/omap-hdm
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/linux/drivers/dma/qcom/
H A Dbam_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 * QCOM BAM DMA engine driver
8 * QCOM BAM DMA blocks are distributed amongst a number of the on-chip
13 * The DMA controller requires the use of external memory for storage of the
19 * During DMA operations, we write descriptors to the FIFO, being careful to
32 #include <linux/dma-mapping.h>
46 #include "../virt-dma.h"
342 #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1)
343 #define BAM_FIFO_SIZE (SZ_32K - 8)
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/linux/sound/soc/dwc/
H A Ddwc-i2s.c47 i2s_write_reg(dev->i2s_base, TER(i), 0); in i2s_disable_channels()
50 i2s_write_reg(dev->i2s_base, RER(i), 0); in i2s_disable_channels()
60 i2s_read_reg(dev->i2s_base, TOR(i)); in i2s_clear_irqs()
63 i2s_read_reg(dev->i2s_base, ROR(i)); in i2s_clear_irqs()
74 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_disable_irqs()
75 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); in i2s_disable_irqs()
79 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_disable_irqs()
80 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); in i2s_disable_irqs()
92 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_enable_irqs()
93 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); in i2s_enable_irqs()
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