Home
last modified time | relevance | path

Searched +full:dma +full:- +full:channel (Results 1 – 25 of 1030) sorted by relevance

12345678910>>...42

/linux/Documentation/arch/arm/stm32/
H A Dstm32-dma-mdma-chaining.rst1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
15 direct memory access controllers (DMA).
17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
18 request routing capabilities are enhanced by a DMA request multiplexer
23 STM32 DMAMUX routes any DMA request from a given peripheral to any STM32 DMA
24 controller (STM32MP1 counts two STM32 DMA controllers) channels.
26 **STM32 DMA**
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dcirrus,ep9301-dma-m2p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic ep93xx SoC M2P DMA controller
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2p
20 - items:
[all …]
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
32 10: Multi-Channel Display Engine MCDE RX
[all …]
H A Dk3dma.txt1 * Hisilicon K3 DMA controller
3 See dma.txt first
6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
[all …]
H A Dingenic,dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs DMA Controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: dma-controller.yaml#
18 - enum:
19 - ingenic,jz4740-dma
20 - ingenic,jz4725b-dma
[all …]
H A Dcirrus,ep9301-dma-m2m.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2m.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic ep93xx SoC DMA controller
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2m
20 - items:
[all …]
/linux/include/linux/dma/
H A Dsprd-dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
16 * we can request 2 dma channels, one for source channel, and another one for
17 * destination channel. Each channel is independent, and has its own
18 * configurations. Once the source channel's transaction is done, it will
19 * trigger the destination channel's transaction automatically by hardware
22 * To support 2-stage tansfer, we must configure the channel mode and trigger
27 * enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
28 * @SPRD_DMA_CHN_MODE_NONE: No channel mode setting which means channel doesn't
29 * support the 2-stage transfer.
[all …]
/linux/arch/arm/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This is the maximum virtual address which can be DMA'd from.
13 arm_dma_zone_size && arm_dma_zone_size < (0x100000000ULL - PAGE_OFFSET) ? \
22 * This is used to support drivers written for the x86 ISA DMA API.
23 * It should not be re-used except for that purpose.
28 #include <mach/isa-dma.h>
31 * The DMA modes reflect the settings for the ISA DMA controller
54 /* Clear the 'DMA Pointer Flip Flop'.
66 /* Request a DMA channel
72 /* Free a DMA channel
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Delo3-dma-0.dtsi2 * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ]
35 dma0: dma@100300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
[all …]
H A Delo3-dma-1.dtsi2 * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ]
35 dma1: dma@101300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
[all …]
H A Delo3-dma-2.dtsi2 * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
35 dma2: dma@102300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
[all …]
H A Dmpc8641si-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
22 mcm-law@0 {
[all …]
/linux/Documentation/driver-api/dmaengine/
H A Dclient.rst2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
8 ``Documentation/crypto/async-tx-api.rst``
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
12 DMA Engine. This is applicable only for slave DMA usage only.
14 DMA usage
17 The slave DMA usage consists of following steps:
19 - Allocate a DMA slave channel
21 - Set slave and controller specific parameters
23 - Get a descriptor for transaction
[all …]
/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxilinx_dma.txt2 It can be configured to have one channel or two channels. If configured
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7 target devices. It can be configured to have one channel or two channels.
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
[all …]
/linux/drivers/soc/ti/
H A Dknav_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/dma-direction.h>
109 struct knav_dma_device *dma; member
118 unsigned channel, flow; member
124 #define chan_number(ch) ((ch->direction == DMA_MEM_TO_DEV) ? \
125 ch->channel : ch->flow)
138 if (!memcmp(&chan->cfg, cfg, sizeof(*cfg))) in check_config()
149 spin_lock(&chan->lock); in chan_start()
150 if ((chan->direction == DMA_MEM_TO_DEV) && chan->reg_chan) { in chan_start()
151 if (cfg->u.tx.filt_pswords) in chan_start()
[all …]
/linux/Documentation/core-api/
H A Ddma-isa-lpc.rst2 DMA with ISA and LPC devices
7 This document describes how to do DMA transfers using the old ISA DMA
9 uses the same DMA system so it will be around for quite some time.
12 ------------------------
14 To do ISA style DMA you need to include two headers::
16 #include <linux/dma-mapping.h>
17 #include <asm/dma.h>
19 The first is the generic DMA API used to convert virtual addresses to
20 bus addresses (see Documentation/core-api/dma-api.rst for details).
22 The second contains the routines specific to ISA DMA transfers. Since
[all …]
/linux/drivers/usb/musb/
H A Dmusb_dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * MUSB OTG driver DMA controller abstraction
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
16 * DMA Controller Abstraction
18 * DMA Controllers are abstracted to allow use of a variety of different
19 * implementations of DMA, as allowed by the Inventra USB cores. On the
20 * host side, usbcore sets up the DMA mappings and flushes caches; on the
22 * of a DMA controller driver include:
24 * - Handling the details of moving multiple USB packets
[all …]
/linux/sound/soc/sprd/
H A Dsprd-pcm-compress.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/dma-mapping.h>
6 #include <linux/dma/sprd-dma.h>
14 #include "sprd-pcm-dm
72 struct sprd_compr_dma dma[SPRD_COMPR_DMA_CHANS]; global() member
119 struct sprd_compr_dma *dma = &stream->dma[1]; sprd_platform_compr_dma_complete() local
132 sprd_platform_compr_dma_config(struct snd_soc_component * component,struct snd_compr_stream * cstream,struct snd_compr_params * params,int channel) sprd_platform_compr_dma_config() argument
140 struct sprd_compr_dma *dma = &stream->dma[channel]; sprd_platform_compr_dma_config() local
401 struct sprd_compr_dma *dma = &stream->dma[i]; sprd_platform_compr_free() local
436 struct sprd_compr_dma *dma = &stream->dma[i]; sprd_platform_compr_trigger() local
451 struct sprd_compr_dma *dma = &stream->dma[i]; sprd_platform_compr_trigger() local
462 struct sprd_compr_dma *dma = &stream->dma[i]; sprd_platform_compr_trigger() local
480 struct sprd_compr_dma *dma = &stream->dma[i]; sprd_platform_compr_trigger() local
492 struct sprd_compr_dma *dma = &stream->dma[i]; sprd_platform_compr_trigger() local
[all...]
/linux/arch/arm/mach-omap2/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP2+ DMA driver
5 * Copyright (C) 2003 - 2008 Nokia Corporation
7 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
8 * Graphics DMA and LCD DMA graphics tranformations
10 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
17 * Converted DMA library into platform driver
[all …]
/linux/drivers/dma/
H A Dfsldma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale MPC85xx, MPC83xx DMA Engine support
5 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
12 * DMA engine driver for Freescale MPC8540 DMA controller, which is
14 * The support for MPC8349 DMA controller is also added.
16 * This driver instructs the DMA controller to issue the PCI Read Multiple
18 * command. Please be aware that this setting may result in read pre-fetching
29 #include <linux/dma-mapping.h>
40 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
42 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-admaif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
13 Tx channel and ADMA channel receiving data from AHUB pairs with
14 ADMAIF Rx channel.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
[all …]
H A Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
15 and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
16 playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
17 playback and DMA channel 3 for capture. The developer can choose which
18 DMA controller to use, but the channels themselves are hard-wired. The
[all …]
/linux/sound/pci/
H A Dad1889.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org>
9 #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */
10 #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
12 #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
13 #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
14 #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
17 #define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */
18 #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
19 #define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
[all …]
/linux/drivers/dma/xilinx/
H A Dzynqmp_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for Xilinx ZynqMP DMA Engine
9 #include <linux/dma-mapping.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
25 #define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100)
26 #define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104)
27 #define ZYNQMP_DMA_IER (chan->irq_offset + 0x108)
28 #define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10c)
118 /* Max number of descriptors per channel */
141 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
[all …]
/linux/include/sound/
H A Ddmaengine_pcm.h1 /* SPDX-License-Identifier: GPL-2.0+
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
15 * snd_pcm_substream_to_dma_direction - Get dma_transfer_direction for a PCM
19 * Return: DMA transfer direction
24 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in snd_pcm_substream_to_dma_direction()
48 * The DAI supports packed transfers, eg 2 16-bit samples in a 32-bit word.
50 * the supported sample formats and set the DMA transfe
[all...]

12345678910>>...42