Home
last modified time | relevance | path

Searched +full:display +full:- +full:backend (Results 1 – 25 of 72) sorted by relevance

123

/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-display-backend.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Display Engine Backend
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The display engine backend exposes layers and sprites to the system.
19 - allwinner,sun4i-a10-display-backend
20 - allwinner,sun5i-a13-display-backend
[all …]
H A Dallwinner,sun4i-a10-display-engine.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Display Engine Pipeline
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The display engine pipeline (and its entry point, since it can be
15 either directly the backend or the frontend) is represented as an
18 The Allwinner A10 Display pipeline is composed of several components
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_backend.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
14 #include <linux/dma-mapping.h>
35 /* backend <-> TCON muxing selection done in backend */
55 regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG, in sun4i_backend_apply_color_correction()
59 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i), in sun4i_backend_apply_color_correction()
68 regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG, in sun4i_backend_disable_color_correction()
78 regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG, in sun4i_backend_commit()
83 void sun4i_backend_layer_enable(struct sun4i_backend *backend, in sun4i_backend_layer_enable() argument
96 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, in sun4i_backend_layer_enable()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "DRM Support for Allwinner A10 Display Engine"
13 Display Engine. If M is selected the module will be called
14 sun4i-drm.
39 tristate "Support for Allwinner A10 Display Engine Backend"
44 original Allwinner Display Engine, which has a backend to
46 selected the module will be called sun4i-backend.
49 tristate "Allwinner A31/A64 MIPI-DSI Controller Support"
57 MIPI-DSI support. If M is selected the module will be called
68 have a Display Engine 2.0 contain this controller. If M is
[all …]
H A Dsun4i_tcon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/media-bus-format.h>
48 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector()
50 if (connector->encoder == encoder) { in sun4i_tcon_get_connector()
66 return -EINVAL; in sun4i_tcon_get_pixel_depth()
68 info = &connector->display_info; in sun4i_tcon_get_pixel_depth()
69 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth()
70 return -EINVAL; in sun4i_tcon_get_pixel_depth()
72 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
[all …]
H A Dsun4i_drv.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/dma-mapping.h>
38 args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), 2); in drm_sun4i_gem_dumb_create()
50 .name = "sun4i-drm",
51 .desc = "Allwinner sun4i Display Engine",
72 ret = -ENOMEM; in sun4i_drv_bind()
76 drm->dev_private = drv; in sun4i_drv_bind()
77 INIT_LIST_HEAD(&drv->frontend_list); in sun4i_drv_bind()
78 INIT_LIST_HEAD(&drv->engine_list); in sun4i_drv_bind()
[all …]
/linux/drivers/soc/sunxi/
H A Dsunxi_mbus.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/dma-map-ops.h>
13 * The display engine virtual devices are not strictly speaking
18 "allwinner,sun4i-a10-display-engine",
19 "allwinner,sun5i-a10s-display-engine",
20 "allwinner,sun5i-a13-display-engine",
21 "allwinner,sun6i-a31-display-engine",
22 "allwinner,sun6i-a31s-display-engine",
23 "allwinner,sun7i-a20-display-engine",
24 "allwinner,sun8i-a23-display-engine",
[all …]
/linux/drivers/gpu/drm/xen/
H A Dxen_drm_front.h1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
4 * Xen para-virtual DRM device
6 * Copyright (C) 2016-2018 EPAM Systems Inc.
27 * DOC: Driver modes of operation in terms of display buffers used
29 * Depending on the requirements for the para-virtualized environment, namely
31 * host and guest environments, display buffers can be allocated by either
32 * frontend driver or backend.
42 * hardware can still reach display buffer memory while importing PRIME
47 * DOC: Buffers allocated by the backend
49 * This mode of operation is run-time configured via guest domain configuration
[all …]
H A Dxen_drm_front_kms.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Xen para-virtual DRM device
6 * Copyright (C) 2016-2018 EPAM Systems Inc.
27 * Timeout in ms to wait for frame done event from the backend:
28 * must be a bit more than IO time-out
40 struct xen_drm_front_drm_info *drm_info = fb->dev->dev_private; in fb_destroy()
43 if (drm_dev_enter(fb->dev, &idx)) { in fb_destroy()
44 xen_drm_front_fb_detach(drm_info->front_info, in fb_destroy()
59 struct xen_drm_front_drm_info *drm_info = dev->dev_private; in fb_create()
68 gem_obj = fb->obj[0]; in fb_create()
[all …]
H A Dxen_drm_front.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Xen para-virtual DRM device
6 * Copyright (C) 2016-2018 EPAM Systems Inc.
12 #include <linux/dma-mapping.h>
26 #include <xen/xen-front-pgdir-shbuf.h>
46 dbuf->dbuf_cookie = dbuf_cookie; in dbuf_add_to_list()
47 list_add(&dbuf->list, &front_info->dbuf_list); in dbuf_add_to_list()
56 if (buf->dbuf_cookie == dbuf_cookie) in dbuf_get()
67 if (buf->dbuf_cookie == dbuf_cookie) { in dbuf_free()
68 list_del(&buf->list); in dbuf_free()
[all …]
H A Dxen_drm_front_cfg.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Xen para-virtual DRM device
6 * Copyright (C) 2016-2018 EPAM Systems Inc.
27 connector_path = devm_kasprintf(&front_info->xb_dev->dev, in cfg_connector()
30 return -ENOMEM; in cfg_connector()
34 &connector->width, &connector->height) < 0) { in cfg_connector()
36 connector->width = 0; in cfg_connector()
37 connector->height = 0; in cfg_connector()
38 return -EINVAL; in cfg_connector()
41 connector->xenstore_path = connector_path; in cfg_connector()
[all …]
/linux/include/xen/interface/io/
H A Ddisplif.h1 /* SPDX-License-Identifier: MIT */
5 * Unified display device I/O interface for Xen guest OSes.
7 * Copyright (C) 2016-2017 EPAM Systems Inc.
32 * sophisticated use-cases than a framebuffer device can handle. At the
37 * o better configuration options including multiple display support
42 * Note: display resolution (XenStore's "resolution" property) defines
43 * visible area of the virtual display. At the same time resolution of
44 * the display and frame buffers may differ: buffers can be smaller, equal
45 * or bigger than the visible area. This is to enable use-cases, where backend
46 * may do some post-processing of the display and frame buffers supplied,
[all …]
/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,ethdr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
15 designed for HDR video and graphics conversion in the external display path.
18 output the required HDR or SDR signal to the subsequent display path.
20 one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL.
21 These two function blocks read the pre-programmed registers from DRAM and
[all …]
/linux/Documentation/gpu/
H A Dxen-front.rst2 drm/xen-front Xen para-virtualized frontend driver
5 This frontend driver implements Xen para-virtualized display
6 according to the display protocol described at
9 Driver modes of operation in terms of display buffers used
12 .. kernel-doc:: drivers/gpu/drm/xen/xen_drm_front.h
13 :doc: Driver modes of operation in terms of display buffers used
16 ----------------------------------------
18 .. kernel-doc:: drivers/gpu/drm/xen/xen_drm_front.h
21 Buffers allocated by the backend
22 --------------------------------
[all …]
/linux/drivers/scsi/elx/libefc/
H A Defclib.h1 /* SPDX-License-Identifier: GPL-2.0 */
109 * @display_name: port display name
113 * @p2p_winner: TRUE if we're the point-to-point winner
117 * @tgt_data: target backend private port data
118 * @ini_data: initiator backend private port data
131 * @p2p_port_id: our port id for point-to-point
134 * @p2p_remote_port_id: remote node's port id for point-to-point
182 * @display_name: Node display name
186 * @ini_domain: initiator backend private domain data
187 * @tgt_domain: target backend private domain data
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a23.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
50 #sound-dai-cells = <0>;
51 compatible = "allwinner,sun8i-a23-codec";
55 clock-names = "apb", "codec";
58 dma-names = "rx", "tx";
59 allwinner,codec-analog-controls = <&codec_analog>;
66 compatible = "allwinner,sun8i-a23-display-backend";
[all …]
H A Dsun8i-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp-table-cpu {
50 compatible = "operating-points-v2";
51 opp-shared;
53 opp-120000000 {
54 opp-hz = /bits/ 64 <120000000>;
[all …]
H A Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
[all …]
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
[all …]
H A Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/clock/sun6i-rtc.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
[all …]
/linux/drivers/xen/
H A Dxen-front-pgdir-shbuf.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Xen frontend/backend page directory based shared buffer
22 #include <xen/xen-front-pgdir-shbuf.h>
27 * buffer. This structure is common to many Xen para-virtualized
39 * is allocated by the corresponding backend or frontend.
50 /* Fill page directory according to para-virtual display protocol. */
66 * page directory. Usually this is passed to the backend,
77 if (!buf->grefs) in xen_front_pgdir_shbuf_get_dir_start()
80 return buf->grefs[0]; in xen_front_pgdir_shbuf_get_dir_start()
90 * references onto the backing storage (buf->pages).
[all …]
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_object_types.h2 * SPDX-License-Identifier: MIT
64 * shrink - Perform further backend specific actions to facilate
67 * @flags: Extra flags to control shrinking behaviour in the backend
71 * I915_GEM_OBJECT_SHRINK_WRITEBACK - Try to perform writeback of the
74 * I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT - Don't wait for the object to
75 * idle. Active objects can be considered later. The TTM backend for
94 * adjust_lru - notify that the madvise value was updated
103 * delayed_free - Override the default delayed free implementation
108 * migrate - Migrate object to a different region either for
122 * enum i915_cache_level - The supported GTT caching values for system memory
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_hwmgr.c30 #include <asm/intel-family.h>
180 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), in cast_phw_smu7_power_state()
190 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), in cast_const_phw_smu7_power_state()
198 * smu7_get_mc_microcode_version - Find the MC microcode version and store it in the HwMgr struct
205 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); in smu7_get_mc_microcode_version()
207 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); in smu7_get_mc_microcode_version()
217 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_speed()
228 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_lane_number()
238 * smu7_enable_smc_voltage_controller - Enable voltage control
245 if (hwmgr->chip_id >= CHIP_POLARIS10 && in smu7_enable_smc_voltage_controller()
[all …]
H A Dvega10_hwmgr.c98 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), in cast_phw_vega10_power_state()
108 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), in cast_const_phw_vega10_power_state()
117 struct vega10_hwmgr *data = hwmgr->backend; in vega10_set_default_registry_data()
119 data->registry_data.sclk_dpm_key_disabled = in vega10_set_default_registry_data()
120 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
121 data->registry_data.socclk_dpm_key_disabled = in vega10_set_default_registry_data()
122 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
123 data->registry_data.mclk_dpm_key_disabled = in vega10_set_default_registry_data()
124 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
125 data->registry_data.pcie_dpm_key_disabled = in vega10_set_default_registry_data()
[all …]
H A Dsmu8_hwmgr.c27 #include "atom-types.h"
53 if (smu8_magic != hw_ps->magic) in cast_smu8_power_state()
62 if (smu8_magic != hw_ps->magic) in cast_const_smu8_power_state()
73 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_get_eclk_level()
78 for (i = 0; i < (int)ptable->count; i++) { in smu8_get_eclk_level()
79 if (clock <= ptable->entries[i].ecclk) in smu8_get_eclk_level()
86 for (i = ptable->count - 1; i >= 0; i--) { in smu8_get_eclk_level()
87 if (clock >= ptable->entries[i].ecclk) in smu8_get_eclk_level()
104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
109 for (i = 0; i < (int)table->count; i++) { in smu8_get_sclk_level()
[all …]

123