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/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddispc.c10 #define DSS_SUBSYS_NAME "DISPC"
37 #include "dispc.h"
41 /* DISPC */
50 #define REG_GET(dispc, idx, start, end) \ argument
51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
54 dispc_write_reg(dispc, idx, \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
57 /* DISPC has feature id */
102 int (*calc_scaling)(struct dispc_device *dispc,
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H A Ddispc.h10 /* DISPC common registers */
36 /* DISPC overlay registers */
97 /* DISPC up/downsampling FIR filter coefficient structure */
108 /* DISPC manager/channel specific registers */
341 /* DISPC overlay register base addresses */
361 /* DISPC overlay register offsets */
H A Ddss.c267 dispc_pck_free_enable(dss->dispc, 1); in dss_sdi_enable()
297 dispc_lcd_enable_signal(dss->dispc, 1); in dss_sdi_enable()
311 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_enable()
316 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_enable()
323 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_disable()
325 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_disable()
386 dispc_dump_clocks(dss->dispc, s); in dss_debug_dump_clocks()
411 * We always use PRCM clock as the DISPC func clock, except on DSS3, in dss_select_dispc_clk_source()
412 * where we don't have separate DISPC and LCD clock sources. in dss_select_dispc_clk_source()
H A Dhdmi_wp.c154 r = FLD_MOD(r, 1, 7, 7); /* VSYNC_POL to dispc active high */ in hdmi_wp_video_config_interface()
155 r = FLD_MOD(r, 1, 6, 6); /* HSYNC_POL to dispc active high */ in hdmi_wp_video_config_interface()
H A Dbase.c21 return dss->dispc; in dispc_get_dispc()
/linux/drivers/gpu/drm/omapdrm/
H A Domap_irq.c19 /* call with wait_lock and dispc runtime held */
33 dispc_write_irqenable(priv->dispc, irqmask); in omap_irq_update()
87 dispc_mgr_get_framedone_irq(priv->dispc, channel); in omap_irq_enable_framedone()
124 priv->irq_mask |= dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_enable_vblank()
150 priv->irq_mask &= ~dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_disable_vblank()
215 irqstatus = dispc_read_irqstatus(priv->dispc); in omap_irq_handler()
216 dispc_clear_irqstatus(priv->dispc, irqstatus); in omap_irq_handler()
217 dispc_read_irqstatus(priv->dispc); /* flush posted write */ in omap_irq_handler()
225 if (irqstatus & dispc_mgr_get_vsync_irq(priv->dispc, channel)) { in omap_irq_handler()
230 if (irqstatus & dispc_mgr_get_sync_lost_irq(priv->dispc, channel)) in omap_irq_handler()
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H A DKconfig35 dispc, dsi, hdmi and rfbi.
45 <debugfs>/omapdss/dispc_irq for DISPC interrupts, and
115 With this you can make sure that DISPC FCK is at least
120 DISPC FCK. However, the FCK will at minimum be
H A DMakefile22 omapdrm-y += dss/base.o dss/output.o dss/dss.o dss/dispc.o \
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,dra7-dss.txt29 - DISPC
39 DISPC
43 - compatible: "ti,dra7-dispc"
46 - interrupts: the DISPC interrupt
51 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap5-dss.txt18 - DISPC
28 DISPC
32 - compatible: "ti,omap5-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap2-dss.txt22 DISPC
26 - compatible: "ti,omap2-dispc"
29 - interrupts: the DISPC interrupt
32 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap4-dss.txt18 - DISPC
28 DISPC
32 - compatible: "ti,omap4-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap3-dss.txt29 DISPC
33 - compatible: "ti,omap3-dispc"
36 - interrupts: the DISPC interrupt
41 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap-dss.txt11 The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
12 a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
18 DISPC is the display controller, which reads pixels from the memory and outputs
59 dispc@58001000 {
60 compatible = "ti,omap4-dispc";
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A DKconfig24 dispc, dsi, hdmi and rfbi.
33 <debugfs>/omapdss/dispc_irq for DISPC interrupts, and
91 With this you can make sure that DISPC FCK is at least
96 DISPC FCK. However, the FCK will at minimum be
H A DMakefile5 omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o display.o \
9 dispc-compat.o display-sysfs.o
H A Ddispc.h3 * linux/drivers/video/omap2/dss/dispc.h
12 /* DISPC common registers */
33 /* DISPC overlay registers */
94 /* DISPC up/downsampling FIR filter coefficient structure */
105 /* DISPC manager/channel specific registers */
338 /* DISPC overlay register base addresses */
358 /* DISPC overlay register offsets */
H A Ddss.h359 /* DISPC */
373 bool dispc_div_calc(unsigned long dispc,
456 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
H A Dmanager-sysfs.c105 DSSERR("failed to apply dispc config\n"); in manager_display_store()
/linux/drivers/gpu/drm/tidss/
H A Dtidss_irq.c22 dispc_set_irqenable(tidss->dispc, tidss->irq_mask); in tidss_irq_update()
63 irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc); in tidss_irq_handler()
H A Dtidss_irq.h15 * The IRQ status from various DISPC IRQ registers are packed into a single
/linux/arch/arm/mach-omap2/
H A Ddisplay.c55 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
315 * DSS clocks are disabled or DISPC module is reset in dispc_disable_outputs()
H A Domap_hwmod_2xxx_ipblock_data.c18 * 'dispc' class
34 .name = "dispc",
H A Domap_hwmod_3xxx_data.c484 * 'dispc' class
501 .name = "dispc",
2582 * ex. if dispc is handled before dss_core and DSS is enabled in omap3xxx_hwmod_init()
2583 * in bootloader DISPC will be reset with outputs enabled in omap3xxx_hwmod_init()
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5.dtsi512 dispc@0 {
513 compatible = "ti,omap5-dispc";

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