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/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,dra7-dss.txt29 - DISPC
39 DISPC
43 - compatible: "ti,dra7-dispc"
46 - interrupts: the DISPC interrupt
51 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap5-dss.txt18 - DISPC
28 DISPC
32 - compatible: "ti,omap5-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap2-dss.txt22 DISPC
26 - compatible: "ti,omap2-dispc"
29 - interrupts: the DISPC interrupt
32 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap4-dss.txt18 - DISPC
28 DISPC
32 - compatible: "ti,omap4-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap3-dss.txt29 DISPC
33 - compatible: "ti,omap3-dispc"
36 - interrupts: the DISPC interrupt
41 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap-dss.txt11 The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
12 a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
18 DISPC is the display controller, which reads pixels from the memory and outputs
59 dispc@58001000 {
60 compatible = "ti,omap4-dispc";
H A Dti,k2g-dss.yaml26 - description: common DISPC common
64 Input memory (from main memory to dispc) bandwidth limit in
H A Dti,j721e-dss.yaml135 Input memory (from main memory to dispc) bandwidth limit in
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A DKconfig24 dispc, dsi, hdmi and rfbi.
33 <debugfs>/omapdss/dispc_irq for DISPC interrupts, and
91 With this you can make sure that DISPC FCK is at least
96 DISPC FCK. However, the FCK will at minimum be
H A DMakefile5 omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o display.o \
9 dispc-compat.o display-sysfs.o
H A Ddispc.h3 * linux/drivers/video/omap2/dss/dispc.h
12 /* DISPC common registers */
33 /* DISPC overlay registers */
94 /* DISPC up/downsampling FIR filter coefficient structure */
105 /* DISPC manager/channel specific registers */
338 /* DISPC overlay register base addresses */
358 /* DISPC overlay register offsets */
H A Ddss.h359 /* DISPC */
373 bool dispc_div_calc(unsigned long dispc,
456 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
H A Ddsi.c4007 dsi_perf_show(dsidev, "DISPC"); in dsi_handle_framedone()
4031 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and in dsi_framedone_irq_callback()
4079 DSSERR("Failed to calc dispc clocks\n"); in dsi_configure_dispc_clocks()
4424 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, in dsi_cm_calc_hsdiv_cb() argument
4430 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; in dsi_cm_calc_hsdiv_cb()
4432 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max, in dsi_cm_calc_hsdiv_cb()
4528 * When there are no line buffers, DISPC and DSI must have the in dsi_vm_calc_blanking()
4529 * same tput. Otherwise DISPC tput needs to be higher than DSI's. in dsi_vm_calc_blanking()
4570 /* DISPC htot to match the DSI TL */ in dsi_vm_calc_blanking()
4573 /* verify that the DSI and DISPC TLs are the same */ in dsi_vm_calc_blanking()
[all …]
/linux/drivers/gpu/drm/omapdrm/
H A DKconfig35 dispc, dsi, hdmi and rfbi.
45 <debugfs>/omapdss/dispc_irq for DISPC interrupts, and
115 With this you can make sure that DISPC FCK is at least
120 DISPC FCK. However, the FCK will at minimum be
H A DMakefile22 omapdrm-y += dss/base.o dss/output.o dss/dss.o dss/dispc.o \
/linux/Documentation/arch/arm/omap/
H A Ddss.rst25 - Use DISPC to update any of the outputs
27 - OMAP DISPC planes
145 An overlay can be connected to one overlay manager. Also DISPC overlays can be
146 connected only to DISPC overlay managers, and virtual overlays can be only
152 - DISPC TV overlay manager can be only connected to TV display.
154 - DISPC LCD overlay manager can be connected to all displays, except TV
/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddispc.h10 /* DISPC common registers */
36 /* DISPC overlay registers */
97 /* DISPC up/downsampling FIR filter coefficient structure */
108 /* DISPC manager/channel specific registers */
341 /* DISPC overlay register base addresses */
361 /* DISPC overlay register offsets */
H A Dhdmi_wp.c154 r = FLD_MOD(r, 1, 7, 7); /* VSYNC_POL to dispc active high */ in hdmi_wp_video_config_interface()
155 r = FLD_MOD(r, 1, 6, 6); /* HSYNC_POL to dispc active high */ in hdmi_wp_video_config_interface()
H A Dbase.c21 return dss->dispc; in dispc_get_dispc()
/linux/drivers/gpu/drm/tidss/
H A Dtidss_irq.c22 dispc_set_irqenable(tidss->dispc, tidss->irq_mask); in tidss_irq_update()
63 irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc); in tidss_irq_handler()
H A Dtidss_irq.h15 * The IRQ status from various DISPC IRQ registers are packed into a single
H A Dtidss_kms.c129 const u32 *fourccs = dispc_plane_formats(tidss->dispc, &fourccs_len); in tidss_dispc_modeset_init()
/linux/arch/arm/boot/dts/ti/omap/
H A Domap2.dtsi312 dispc@48050400 {
313 compatible = "ti,omap2-dispc";
/linux/arch/arm/mach-omap2/
H A Ddisplay.c55 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
315 * DSS clocks are disabled or DISPC module is reset in dispc_disable_outputs()
H A Domap_hwmod_2xxx_ipblock_data.c18 * 'dispc' class
34 .name = "dispc",

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