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/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddispc.c10 #define DSS_SUBSYS_NAME "DISPC"
37 #include "dispc.h"
41 /* DISPC */
50 #define REG_GET(dispc, idx, start, end) \ argument
51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
54 dispc_write_reg(dispc, idx, \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
57 /* DISPC has feature id */
102 int (*calc_scaling)(struct dispc_device *dispc,
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H A Ddispc.h10 /* DISPC common registers */
36 /* DISPC overlay registers */
97 /* DISPC up/downsampling FIR filter coefficient structure */
108 /* DISPC manager/channel specific registers */
341 /* DISPC overlay register base addresses */
361 /* DISPC overlay register offsets */
H A Ddss.c267 dispc_pck_free_enable(dss->dispc, 1); in dss_sdi_enable()
297 dispc_lcd_enable_signal(dss->dispc, 1); in dss_sdi_enable()
311 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_enable()
316 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_enable()
323 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_disable()
325 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_disable()
386 dispc_dump_clocks(dss->dispc, s); in dss_debug_dump_clocks()
411 * We always use PRCM clock as the DISPC func clock, except on DSS3, in dss_select_dispc_clk_source()
412 * where we don't have separate DISPC and LCD clock sources. in dss_select_dispc_clk_source()
H A Ddsi.c934 dispc_pck_free_enable(dsi->dss->dispc, 1); in dsi_pll_enable()
939 dispc_pck_free_enable(dsi->dss->dispc, 0); in dsi_pll_enable()
945 dispc_pck_free_enable(dsi->dss->dispc, 0); in dsi_pll_enable()
3053 dev_err(dsi->dev, "failed to init dispc!\n"); in dsi_enable_video_output()
3145 dispc_disable_sidle(dsi->dss->dispc); in dsi_update_screen_dispc()
3178 dispc_enable_sidle(dsi->dss->dispc); in dsi_handle_framedone()
3188 dsi_perf_show(dsi, "DISPC"); in dsi_handle_framedone()
3211 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and in dsi_framedone_irq_callback()
3316 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo); in dsi_configure_dispc_clocks()
3318 DSSERR("Failed to calc dispc clocks\n"); in dsi_configure_dispc_clocks()
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/linux/drivers/gpu/drm/omapdrm/
H A Domap_irq.c19 /* call with wait_lock and dispc runtime held */
33 dispc_write_irqenable(priv->dispc, irqmask); in omap_irq_update()
87 dispc_mgr_get_framedone_irq(priv->dispc, channel); in omap_irq_enable_framedone()
124 priv->irq_mask |= dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_enable_vblank()
150 priv->irq_mask &= ~dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_disable_vblank()
215 irqstatus = dispc_read_irqstatus(priv->dispc); in omap_irq_handler()
216 dispc_clear_irqstatus(priv->dispc, irqstatus); in omap_irq_handler()
217 dispc_read_irqstatus(priv->dispc); /* flush posted write */ in omap_irq_handler()
225 if (irqstatus & dispc_mgr_get_vsync_irq(priv->dispc, channel)) { in omap_irq_handler()
230 if (irqstatus & dispc_mgr_get_sync_lost_irq(priv->dispc, channel)) in omap_irq_handler()
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H A Domap_crtc.c106 dispc_mgr_enable(priv->dispc, channel, true); in omap_crtc_dss_start_update()
131 dispc_mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
144 framedone_irq = dispc_mgr_get_framedone_irq(priv->dispc, in omap_crtc_set_enabled()
146 vsync_irq = dispc_mgr_get_vsync_irq(priv->dispc, channel); in omap_crtc_set_enabled()
153 * FRAMEDONE to know that DISPC has finished with the output. in omap_crtc_set_enabled()
166 dispc_mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
188 dispc_mgr_set_timings(priv->dispc, omap_crtc->channel, in omap_crtc_dss_enable()
222 dispc_mgr_set_lcd_config(priv->dispc, omap_crtc->channel, in omap_crtc_dss_set_lcd_config()
288 * If the dispc is busy we're racing the flush operation. Try again on in omap_crtc_vblank_irq()
291 if (dispc_mgr_go_busy(priv->dispc, omap_crtc->channel)) { in omap_crtc_vblank_irq()
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H A Domap_plane.c141 ret = dispc_ovl_setup(priv->dispc, ovl_id, &info, in omap_plane_atomic_update()
147 dispc_ovl_enable(priv->dispc, ovl_id, false); in omap_plane_atomic_update()
151 dispc_ovl_enable(priv->dispc, ovl_id, true); in omap_plane_atomic_update()
154 ret = dispc_ovl_setup(priv->dispc, r_ovl_id, &r_info, in omap_plane_atomic_update()
160 dispc_ovl_enable(priv->dispc, r_ovl_id, false); in omap_plane_atomic_update()
161 dispc_ovl_enable(priv->dispc, ovl_id, false); in omap_plane_atomic_update()
165 dispc_ovl_enable(priv->dispc, r_ovl_id, true); in omap_plane_atomic_update()
225 dispc_ovl_get_max_size(priv->dispc, &width, &height); in omap_plane_atomic_check()
242 * phase in dispc. in omap_plane_atomic_check()
317 if (!dispc_ovl_color_mode_supported(priv->dispc, omap_state->overlay->id, in omap_plane_atomic_check()
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H A DKconfig35 dispc, dsi, hdmi and rfbi.
45 <debugfs>/omapdss/dispc_irq for DISPC interrupts, and
115 With this you can make sure that DISPC FCK is at least
120 DISPC FCK. However, the FCK will at minimum be
H A Domap_drv.c73 dispc_runtime_get(priv->dispc); in omap_atomic_commit_tail()
79 /* With the current dss dispc implementation we have to enable in omap_atomic_commit_tail()
80 * the new modeset before we can commit planes. The dispc ovl in omap_atomic_commit_tail()
87 * interrupt. The dispc implementation should be fixed so that in omap_atomic_commit_tail()
117 dispc_runtime_put(priv->dispc); in omap_atomic_commit_tail()
367 unsigned int num_planes = dispc_get_num_ovls(priv->dispc); in omap_modeset_init_properties()
394 int num_ovls = dispc_get_num_ovls(priv->dispc); in omap_modeset_init()
395 int num_mgrs = dispc_get_num_mgrs(priv->dispc); in omap_modeset_init()
473 * Populate the pipeline lookup table by DISPC channel. Only one display in omap_modeset_init()
689 priv->dispc = dispc_get_dispc(priv->dss); in omapdrm_init()
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H A Domap_overlay.c51 if (!dispc_ovl_color_mode_supported(priv->dispc, in omap_plane_find_free_overlay()
148 dispc_ovl_enable(priv->dispc, overlay->id, false); in omap_overlay_update_state()
179 u32 num_overlays = dispc_get_num_ovls(priv->dispc); in omap_hwoverlays_init()
186 caps = dispc_ovl_get_caps(priv->dispc, hw_plane_ids[i]); in omap_hwoverlays_init()
/linux/drivers/gpu/drm/tidss/
H A Dtidss_crtc.c38 busy = dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_finish_page_flip()
92 struct dispc_device *dispc = tidss->dispc; in tidss_crtc_atomic_check() local
103 ok = dispc_vp_mode_valid(dispc, hw_videoport, mode); in tidss_crtc_atomic_check()
113 return dispc_vp_bus_check(dispc, hw_videoport, crtc_state); in tidss_crtc_atomic_check()
154 dispc_ovr_set_plane(tidss->dispc, tplane->hw_plane_id, in tidss_crtc_position_planes()
159 dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer, in tidss_crtc_position_planes()
187 if (WARN_ON(dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport))) in tidss_crtc_atomic_flush()
195 dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, false); in tidss_crtc_atomic_flush()
203 dispc_vp_go(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_atomic_flush()
229 r = dispc_vp_set_clk_rate(tidss->dispc, tcrtc->hw_videoport, in tidss_crtc_atomic_enable()
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H A Dtidss_plane.c107 ret = dispc_plane_check(tidss->dispc, hw_plane, new_plane_state, in tidss_plane_atomic_check()
126 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_update()
132 dispc_plane_setup(tidss->dispc, tplane->hw_plane_id, new_state, hw_videoport); in tidss_plane_atomic_update()
142 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true); in tidss_plane_atomic_enable()
152 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_disable()
H A Dtidss_irq.c22 dispc_set_irqenable(tidss->dispc, tidss->irq_mask); in tidss_irq_update()
63 irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc); in tidss_irq_handler()
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,dra7-dss.txt29 - DISPC
39 DISPC
43 - compatible: "ti,dra7-dispc"
46 - interrupts: the DISPC interrupt
51 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap5-dss.txt18 - DISPC
28 DISPC
32 - compatible: "ti,omap5-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap2-dss.txt22 DISPC
26 - compatible: "ti,omap2-dispc"
29 - interrupts: the DISPC interrupt
32 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap4-dss.txt18 - DISPC
28 DISPC
32 - compatible: "ti,omap4-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap3-dss.txt29 DISPC
33 - compatible: "ti,omap3-dispc"
36 - interrupts: the DISPC interrupt
41 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap-dss.txt11 The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
12 a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
18 DISPC is the display controller, which reads pixels from the memory and outputs
59 dispc@58001000 {
60 compatible = "ti,omap4-dispc";
H A Dti,k2g-dss.yaml26 - description: common DISPC common
64 Input memory (from main memory to dispc) bandwidth limit in
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A DKconfig24 dispc, dsi, hdmi and rfbi.
33 <debugfs>/omapdss/dispc_irq for DISPC interrupts, and
91 With this you can make sure that DISPC FCK is at least
96 DISPC FCK. However, the FCK will at minimum be
H A Ddispc.h3 * linux/drivers/video/omap2/dss/dispc.h
12 /* DISPC common registers */
33 /* DISPC overlay registers */
94 /* DISPC up/downsampling FIR filter coefficient structure */
105 /* DISPC manager/channel specific registers */
338 /* DISPC overlay register base addresses */
358 /* DISPC overlay register offsets */
H A DMakefile5 omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o display.o \
9 dispc-compat.o display-sysfs.o
H A Ddss.h359 /* DISPC */
373 bool dispc_div_calc(unsigned long dispc,
456 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
/linux/Documentation/arch/arm/omap/
H A Ddss.rst25 - Use DISPC to update any of the outputs
27 - OMAP DISPC planes
145 An overlay can be connected to one overlay manager. Also DISPC overlays can be
146 connected only to DISPC overlay managers, and virtual overlays can be only
152 - DISPC TV overlay manager can be only connected to TV display.
154 - DISPC LCD overlay manager can be connected to all displays, except TV

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