Searched full:disp_cc_mdss_core_bcr (Results 1 – 25 of 28) sorted by relevance
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | qcom,dispcc-qcm2290.h | 36 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,sm6375-dispcc.h | 36 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,sm4450-dispcc.h | 47 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,qcs615-dispcc.h | 49 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,milos-dispcc.h | 53 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,dispcc-sm8150.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,dispcc-sm8250.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,dispcc-sm8350.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,x1e80100-dispcc.h | 90 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,dispcc-sc8280xp.h | 93 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,sm8450-dispcc.h | 95 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,sm8550-dispcc.h | 93 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,sm8650-dispcc.h | 93 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,sm8750-dispcc.h | 104 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| /freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
| H A D | qcom,sc8280xp-mdss.yaml | 77 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
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| H A D | qcom,sm8350-mdss.yaml | 111 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | qcom,sm8450-mdss.yaml | 101 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | qcom,sm8550-mdss.yaml | 102 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | qcom,sm8750-mdss.yaml | 104 resets = <&disp_cc_mdss_core_bcr>;
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | qcm2290.dtsi | 1749 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | sc8280xp.dtsi | 4230 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
5562 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
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| H A D | sar2130p.dtsi | 2035 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | sm8350.dtsi | 2762 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | sc8180x.dtsi | 2959 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | sm8450.dtsi | 3316 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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