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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dqcom,dispcc-qcm2290.h16 #define DISP_CC_MDSS_BYTE0_INTF_CLK 6 macro
H A Dqcom,sm6115-dispcc.h17 #define DISP_CC_MDSS_BYTE0_INTF_CLK 7 macro
H A Dqcom,dispcc-sm6125.h14 #define DISP_CC_MDSS_BYTE0_INTF_CLK 5 macro
H A Dqcom,sm6375-dispcc.h17 #define DISP_CC_MDSS_BYTE0_INTF_CLK 6 macro
H A Dqcom,dispcc-sc7180.h16 #define DISP_CC_MDSS_BYTE0_INTF_CLK 7 macro
H A Dqcom,dispcc-sm6350.h17 #define DISP_CC_MDSS_BYTE0_INTF_CLK 6 macro
H A Dqcom,sm4450-dispcc.h16 #define DISP_CC_MDSS_BYTE0_INTF_CLK 6 macro
H A Dqcom,dispcc-sc7280.h16 #define DISP_CC_MDSS_BYTE0_INTF_CLK 6 macro
H A Dqcom,dispcc-sdm845.h14 #define DISP_CC_MDSS_BYTE0_INTF_CLK 4 macro
H A Dqcom,qcs615-dispcc.h15 #define DISP_CC_MDSS_BYTE0_INTF_CLK 5 macro
H A Dqcom,milos-dispcc.h19 #define DISP_CC_MDSS_BYTE0_INTF_CLK 8 macro
H A Dqcom,dispcc-sm8150.h15 #define DISP_CC_MDSS_BYTE0_INTF_CLK 5 macro
H A Dqcom,dispcc-sm8250.h15 #define DISP_CC_MDSS_BYTE0_INTF_CLK 5 macro
H A Dqcom,dispcc-sm8350.h15 #define DISP_CC_MDSS_BYTE0_INTF_CLK 5 macro
H A Dqcom,x1e80100-dispcc.h17 #define DISP_CC_MDSS_BYTE0_INTF_CLK 7 macro
H A Dqcom,dispcc-sc8280xp.h20 #define DISP_CC_MDSS_BYTE0_INTF_CLK 10 macro
H A Dqcom,sm8450-dispcc.h16 #define DISP_CC_MDSS_BYTE0_INTF_CLK 6 macro
H A Dqcom,sm8550-dispcc.h17 #define DISP_CC_MDSS_BYTE0_INTF_CLK 7 macro
H A Dqcom,sm8650-dispcc.h17 #define DISP_CC_MDSS_BYTE0_INTF_CLK 7 macro
H A Dqcom,sm8750-dispcc.h23 #define DISP_CC_MDSS_BYTE0_INTF_CLK 11 macro
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dqcom,qcm2290-mdss.yaml156 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
H A Dqcom,sm6115-mdss.yaml147 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
H A Dqcom,sm6375-mdss.yaml157 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
H A Dqcom,sm6350-mdss.yaml165 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
H A Dqcom,sm8350-mdss.yaml203 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,

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