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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
H A Ddcn21_hwseq.c43 hws->ctx
45 hws->regs->reg
49 hws->shifts->field_name, hws->masks->field_name
63 …config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_… in mmhub_update_page_table_config()
67 int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_co… in dcn21_init_sys_ctx() argument
71 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; in dcn21_init_sys_ctx()
72 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; in dcn21_init_sys_ctx()
73 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; in dcn21_init_sys_ctx()
74 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; in dcn21_init_sys_ctx()
75 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; in dcn21_init_sys_ctx()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.c1 // SPDX-License-Identifier: MIT
61 hws->ctx
63 hws->regs->reg
65 stream->ctx->logger
70 hws->shifts->field_name, hws->masks->field_name
74 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream()
75 struct dc_stream_state *stream = pipe_ctx->stream; in update_dsc_on_stream()
80 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in update_dsc_on_stream()
89 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in update_dsc_on_stream()
90 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in update_dsc_on_stream()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c66 hws->ctx
68 hws->regs->reg
72 hws->shifts->field_name, hws->masks->field_name
74 void dcn20_log_color_state(struct dc *dc, in dcn20_log_color_state() argument
77 struct dc_context *dc_ctx = dc->ctx; in dcn20_log_color_state()
78 struct resource_pool *pool = dc->res_pool; in dcn20_log_color_state()
87 for (i = 0; i < pool->pipe_count; i++) { in dcn20_log_color_state()
88 struct dpp *dpp = pool->dpps[i]; in dcn20_log_color_state()
91 dpp->funcs->dpp_read_state(dpp, &s); in dcn20_log_color_state()
92 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); in dcn20_log_color_state()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c61 hws->ctx
63 hws->regs->reg
65 dc->ctx->logger
70 hws->shifts->field_name, hws->masks->field_name
72 void dcn30_log_color_state(struct dc *dc, in dcn30_log_color_state() argument
75 struct dc_context *dc_ctx = dc->ctx; in dcn30_log_color_state()
76 struct resource_pool *pool = dc->res_pool; in dcn30_log_color_state()
86 for (i = 0; i < pool->pipe_count; i++) { in dcn30_log_color_state()
87 struct dpp *dpp = pool->dpps[i]; in dcn30_log_color_state()
90 dpp->funcs->dpp_read_state(dpp, &s); in dcn30_log_color_state()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c1 /* SPDX-License-Identifier: MIT */
65 hws->ctx
67 hws->regs->reg
74 hws->shifts->field_name, hws->masks->field_name
76 static void enable_memory_low_power(struct dc *dc)
78 struct dce_hwseq *hws = dc->hwseq;
81 if (dc->debug.enable_mem_low_power.bits.dmcu) {
83 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
89 if (dc->debug.enable_mem_low_power.bits.optc) {
94 if (dc->debug.enable_mem_low_power.bits.vga) {
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/linux/drivers/tty/
H A Dnozomi.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * nozomi.c -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
18 * --------------------------------------------------------------------------
25 * --------------------------------------------------------------------------
132 F32_2 = 2048, /* 512 bytes downlink + uplink * 2 -> 2048 */
133 F32_8 = 8192, /* 3072 bytes downl. + 1024 bytes uplink * 2 -> 8192 */
157 CTRL_ERROR = -1,
167 PORT_ERROR = -1,
176 * else A-channels must always be used.
246 * else A-channels must always be used.
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
108 // for example, 1080p -> 8K is 4.0, or 4000 raw value
116 // for example, 8K -> 1080p is 0.25, or 250 raw value
128 * DOC: color-management-caps
133 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
140 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
156 * struct dpp_color_caps - color pipeline capabilities for display pipe and
161 * just plain 256-entry lookup
170 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
171 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
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/linux/drivers/gpu/drm/bridge/imx/
H A Dimx8qxp-pixel-link.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/media-bus-format.h>
18 #include <dt-bindings/firmware/imx/rsrc.h>
20 #define DRIVER_NAME "imx8qxp-display-pixel-link"
43 ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, in imx8qxp_pixel_link_enable_mst_en()
44 pl->mst_en_ctrl, true); in imx8qxp_pixel_link_enable_mst_en()
46 DRM_DEV_ERROR(pl->dev, in imx8qxp_pixel_link_enable_mst_en()
47 "failed to enable DC%u stream%u pixel link mst_en: %d\n", in imx8qxp_pixel_link_enable_mst_en()
48 pl->dc_id, pl->stream_id, ret); in imx8qxp_pixel_link_enable_mst_en()
55 ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, in imx8qxp_pixel_link_enable_mst_vld()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c57 hws->ctx
59 hws->regs->reg
61 dc->ctx->logger
66 hws->shifts->field_name, hws->masks->field_name
68 static void enable_memory_low_power(struct dc *dc) in enable_memory_low_power() argument
70 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power()
73 if (dc->debug.enable_mem_low_power.bits.dmcu) { in enable_memory_low_power()
75 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { in enable_memory_low_power()
81 if (dc->debug.enable_mem_low_power.bits.optc) { in enable_memory_low_power()
86 if (dc->debug.enable_mem_low_power.bits.vga) { in enable_memory_low_power()
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/
H A Ddcn401_optc.c1 // SPDX-License-Identifier: MIT
10 #include "dc.h"
15 optc1->tg_regs->reg
18 optc1->base.ctx
22 optc1->tg_shift->field_name, optc1->tg_mask->field_name
108 uint32_t h_active = segment_width * (opp_cnt - 1) + last_segment_width; in optc401_set_odm_combine()
162 optc1->opp_count = opp_cnt; in optc401_set_odm_combine()
173 * optc401_enable_crtc() - Enable CRTC
186 OPTC_SEG0_SRC_SEL, optc->inst); in optc401_enable_crtc()
220 /* disable otg request until end of the first line in optc401_disable_crtc()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_replay.c28 #include "dc.h"
33 #include "dc/inc/link.h"
36 * amdgpu_dm_link_supports_replay() - check if the link supports replay
43 struct dm_connector_state *state = to_dm_connector_state(aconnector->base.state); in amdgpu_dm_link_supports_replay()
44 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; in amdgpu_dm_link_supports_replay()
45 struct adaptive_sync_caps *as_caps = &link->dpcd_caps.adaptive_sync_caps; in amdgpu_dm_link_supports_replay()
47 if (!state->freesync_capable) in amdgpu_dm_link_supports_replay()
50 if (!aconnector->vsdb_info.replay_mode) in amdgpu_dm_link_supports_replay()
54 if (dpcd_caps->edp_rev < EDP_REVISION_13) in amdgpu_dm_link_supports_replay()
57 if (!dpcd_caps->alpm_caps.bits.AUX_WAKE_ALPM_CAP) in amdgpu_dm_link_supports_replay()
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H A Damdgpu_dm_psr.c28 #include "dc.h"
35 struct dc *dc = link->ctx->dc; in link_supports_psrsu() local
37 if (!dc->caps.dmcub_support) in link_supports_psrsu()
40 if (dc->ctx->dce_version < DCN_VERSION_3_1) in link_supports_psrsu()
46 if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP || in link_supports_psrsu()
47 !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) in link_supports_psrsu()
50 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED && in link_supports_psrsu()
51 !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap) in link_supports_psrsu()
57 return dc_dmub_check_min_version(dc->ctx->dmub_srv->dmub); in link_supports_psrsu()
61 * amdgpu_dm_set_psr_caps() - set link psr capabilities
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H A Damdgpu_dm_crtc.c1 // SPDX-License-Identifier: MIT
29 #include "dc.h"
43 struct drm_crtc *crtc = &acrtc->base; in amdgpu_dm_crtc_handle_vblank()
44 struct drm_device *dev = crtc->dev; in amdgpu_dm_crtc_handle_vblank()
49 spin_lock_irqsave(&dev->event_lock, flags); in amdgpu_dm_crtc_handle_vblank()
51 /* Send completion event for cursor-only commits */ in amdgpu_dm_crtc_handle_vblank()
52 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { in amdgpu_dm_crtc_handle_vblank()
53 drm_crtc_send_vblank_event(crtc, acrtc->event); in amdgpu_dm_crtc_handle_vblank()
55 acrtc->event = NULL; in amdgpu_dm_crtc_handle_vblank()
58 spin_unlock_irqrestore(&dev->event_lock, flags); in amdgpu_dm_crtc_handle_vblank()
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/linux/Documentation/ABI/testing/
H A Dsysfs-driver-qat4 Contact: qat-linux@intel.com
22 Contact: qat-linux@intel.com
31 * dc: the device is configured for running compression services
32 * dcc: identical to dc but enables the dc chaining feature,
33 hash then compression. If this is not required chose dc
38 * asym;dc: the device is configured for running asymmetric
40 * dc;asym: identical to asym;dc
41 * sym;dc: the device is configured for running symmetric crypto
43 * dc;sym: identical to sym;dc
57 # echo dc > /sys/bus/pci/devices/<BDF>/qat/cfg_services
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c59 hws->ctx
61 hws->regs->reg
63 dc->ctx->logger
67 hws->shifts->field_name, hws->masks->field_name
77 struct dc *dc = hws->ctx->dc; in dcn32_dsc_pg_control() local
79 if (dc->debug.disable_dsc_power_gate) in dcn32_dsc_pg_control()
82 if (!dc->debug.enable_double_buffered_dsc_pg_support) in dcn32_dsc_pg_control()
89 DC_LOG_DSC("%s DSC power gate for inst %d", power_gate ? "enable" : "disable", dsc_inst); in dcn32_dsc_pg_control()
137 bool force_on = true; /* disable power gating */ in dcn32_enable_power_gating_plane()
168 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn32_hubp_pg_control()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c1 // SPDX-License-Identifier: MIT
40 hws->ctx
42 hws->regs->reg
44 dc->ctx->logger
49 hws->shifts->field_name, hws->masks->field_name
51 static void dcn401_initialize_min_clocks(struct dc *dc) in dcn401_initialize_min_clocks() argument
53 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
55 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; in dcn401_initialize_min_clocks()
56 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
57 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
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/linux/drivers/power/supply/
H A Dmax8903_charger.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * max8903_charger.c - Maxim 8903 USB/Adapter Charger Driver
28 struct gpio_desc *dok; /* DC (Adapter) Power OK output */
32 struct gpio_desc *dcm; /* Current-Limit Mode input (1: DC, 2: USB) */
53 val->intval = POWER_SUPPLY_STATUS_UNKNOWN; in max8903_get_property()
54 if (data->chg) { in max8903_get_property()
55 if (gpiod_get_value(data->chg)) in max8903_get_property()
57 val->intval = POWER_SUPPLY_STATUS_CHARGING; in max8903_get_property()
58 else if (data->usb_in || data->ta_in) in max8903_get_property()
59 val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; in max8903_get_property()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c67 hws->ctx
69 hws->regs->reg
73 hws->shifts->field_name, hws->masks->field_name
88 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
97 void dcn10_lock_all_pipes(struct dc *dc, in dcn10_lock_all_pipes() argument
106 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
107 old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
108 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
109 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
115 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
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/linux/Documentation/devicetree/bindings/power/supply/
H A Dqcom,pm8941-charger.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/qcom,pm8941-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Switch-Mode Battery Charger and Boost
10 - Sebastian Reichel <sre@kernel.org>
15 - qcom,pm8226-charger
16 - qcom,pm8941-charger
23 - description: charge done
24 - description: charge fast mode
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/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_phy.c27 * This file implements basic dp phy functionality such as enable/disable phy
42 link->ctx->logger
50 if (link->sync_lt_in_progress) in dpcd_write_rx_power_ctrl()
65 link->cur_link_settings = *link_settings; in dp_enable_link_phy()
66 link->dc->hwss.enable_dp_link_output(link, link_res, signal, in dp_enable_link_phy()
75 struct dc *dc = link->ctx->dc; in dp_disable_link_phy() local
77 if (!link->wa_flags.dp_keep_receiver_powered && in dp_disable_link_phy()
78 !link->skip_implict_edp_power_control) in dp_disable_link_phy()
81 dc->hwss.disable_link_output(link, link_res, signal); in dp_disable_link_phy()
83 memset(&link->cur_link_settings, 0, in dp_disable_link_phy()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c27 #include "dc.h"
74 * For eDP, after power-up/power/down,
84 hws->ctx
87 ctx->logger
89 struct dc_context *ctx = dc->ctx
92 hws->regs->reg
96 hws->shifts->field_name, hws->masks->field_name
104 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
107 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
110 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn32/
H A Ddcn32_optc.c31 #include "dc.h"
36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
96 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine()
97 optc1->opp_count = opp_cnt; in optc32_set_odm_combine()
120 *odm_combine_segments = -1; in optc32_get_odm_combine_segments()
139 * optc32_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
151 OPTC_SEG0_SRC_SEL, optc->inst); in optc32_enable_crtc()
185 /* disable otg request until end of the first line in optc32_disable_crtc()
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/linux/arch/sparc/include/asm/
H A Dfhc.h1 /* SPDX-License-Identifier: GPL-2.0 */
42 #define FHC_CONTROL_LFAT 0x00040000 /* AC/DC signalled a local error */
44 #define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
45 #define FHC_CONTROL_POFF 0x00004000 /* AC/DC Controller PLL Disable */
46 #define FHC_CONTROL_FOFF 0x00002000 /* FHC Controller PLL Disable */
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c29 #include "dc.h"
90 dc->ctx
93 dc->ctx->logger
95 static const char DC_BUILD_ID[] = "production-build";
100 * DC is the OS-agnostic component of the amdgpu DC driver.
102 * DC maintains and validates a set of structs representing the state of the
105 * Main DC HW structs:
107 * struct dc - The central struct. One per driver. Created on driver load,
110 * struct dc_context - One per driver.
111 * Used as a backpointer by most other structs in dc.
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/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ad5755.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
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