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1 // SPDX-License-Identifier: GPL-2.0-or-later12 #include <linux/mmc/slot-gpio.h>17 #include "dw_mmc-pltfm.h"42 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to47 unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; in rockchip_mmc_get_internal_phase()79 struct dw_mci_rockchip_priv_data *priv = host->priv; in rockchip_mmc_get_phase()80 struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; in rockchip_mmc_get_phase()82 if (priv->internal_phase) in rockchip_mmc_get_phase()90 unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; in rockchip_mmc_set_internal_phase()109 dev_err(host->dev, "%s: invalid clk rate\n", __func__); in rockchip_mmc_set_internal_phase()[all …]