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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dvelintrin_gen.h1 #define _vel_vld_vssl __builtin_ve_vl_vld_vssl
2 #define _vel_vld_vssvl __builtin_ve_vl_vld_vssvl
3 #define _vel_vldnc_vssl __builtin_ve_vl_vldnc_vssl
4 #define _vel_vldnc_vssvl __builtin_ve_vl_vldnc_vssvl
5 #define _vel_vldu_vssl __builtin_ve_vl_vldu_vssl
6 #define _vel_vldu_vssvl __builtin_ve_vl_vldu_vssvl
7 #define _vel_vldunc_vssl __builtin_ve_vl_vldunc_vssl
8 #define _vel_vldunc_vssvl __builtin_ve_vl_vldunc_vssvl
9 #define _vel_vldlsx_vssl __builtin_ve_vl_vldlsx_vssl
10 #define _vel_vldlsx_vssvl __builtin_ve_vl_vldlsx_vssvl
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/freebsd/crypto/openssl/util/
H A Dother.syms2 # that don't appear in lib*.num -- because they are define's, in
147 ASN1_BIT_STRING_digest define
148 BIO_append_filename define
149 BIO_destroy_bio_pair define
150 BIO_ctrl_dgram_connect define
151 BIO_ctrl_set_connected define
152 BIO_dgram_get_mtu_overhead define
153 BIO_dgram_get_peer define
154 BIO_dgram_set_peer define
155 BIO_dgram_recv_timedout define
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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dexynos5433.h8 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H
11 #define CLK_FOUT_ISP_PLL 1
12 #define CLK_FOUT_AUD_PLL 2
14 #define CLK_MOUT_AUD_PLL 10
15 #define CLK_MOUT_ISP_PLL 11
16 #define CLK_MOUT_AUD_PLL_USER_T 12
17 #define CLK_MOUT_MPHY_PLL_USER 13
18 #define CLK_MOUT_MFC_PLL_USER 14
19 #define CLK_MOUT_BUS_PLL_USER 15
20 #define CLK_MOUT_ACLK_HEVC_40
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H A Drockchip,rk3588-cru.h11 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
15 #define PLL_B0PLL 0
16 #define PLL_B1PLL 1
17 #define PLL_LPLL 2
18 #define PLL_V0PLL 3
19 #define PLL_AUPLL 4
20 #define PLL_CPLL 5
21 #define PLL_GPLL 6
22 #define PLL_NPLL 7
23 #define PLL_PPLL 8
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H A Dmt8195-clk.h8 #define _DT_BINDINGS_CLK_MT8195_H
12 #define CLK_TOP_AXI 0
13 #define CLK_TOP_SPM 1
14 #define CLK_TOP_SCP 2
15 #define CLK_TOP_BUS_AXIMEM 3
16 #define CLK_TOP_VPP 4
17 #define CLK_TOP_ETHDR 5
18 #define CLK_TOP_IPE 6
19 #define CLK_TOP_CAM 7
20 #define CLK_TOP_CCU 8
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H A Drk3568-cru.h8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
13 #define PLL_PPLL 1
14 #define PLL_HPLL 2
17 #define XIN_OSC0_DIV 4
18 #define CLK_RTC_32K 5
19 #define CLK_PMU 6
20 #define CLK_I2C0 7
21 #define CLK_RTC32K_FRAC 8
22 #define CLK_UART0_DIV 9
23 #define CLK_UART0_FRAC 10
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H A Dmediatek,mt8188-clk.h8 #define _DT_BINDINGS_CLK_MT8188_H
11 #define CLK_TOP_AXI 0
12 #define CLK_TOP_SPM 1
13 #define CLK_TOP_SCP 2
14 #define CLK_TOP_BUS_AXIMEM 3
15 #define CLK_TOP_VPP 4
16 #define CLK_TOP_ETHDR 5
17 #define CLK_TOP_IPE 6
18 #define CLK_TOP_CAM 7
19 #define CLK_TOP_CCU 8
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H A Dgoogle,gs101.h10 #define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
13 #define CLK_FOUT_SHARED0_PLL 1
14 #define CLK_FOUT_SHARED1_PLL 2
15 #define CLK_FOUT_SHARED2_PLL 3
16 #define CLK_FOUT_SHARED3_PLL 4
17 #define CLK_FOUT_SPARE_PLL 5
20 #define CLK_MOUT_PLL_SHARED0 6
21 #define CLK_MOUT_PLL_SHARED1 7
22 #define CLK_MOUT_PLL_SHARED2 8
23 #define CLK_MOUT_PLL_SHARED3 9
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H A Drk3399-cru.h8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
11 #define PLL_APLLL 1
12 #define PLL_APLLB 2
13 #define PLL_DPLL 3
14 #define PLL_CPLL 4
15 #define PLL_GPLL 5
16 #define PLL_NPLL 6
17 #define PLL_VPLL 7
18 #define ARMCLKL 8
19 #define ARMCLKB 9
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H A Drockchip,rk3576-cru.h11 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
16 #define PLL_BPLL 0
17 #define PLL_LPLL 1
18 #define PLL_VPLL 2
19 #define PLL_AUPLL 3
20 #define PLL_CPLL 4
21 #define PLL_GPLL 5
22 #define PLL_PPLL 6
23 #define ARMCLK_L 7
24 #define ARMCLK_B 8
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H A Drockchip,rv1126-cru.h8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
13 #define PLL_GPLL 1
16 #define CLK_OSC0_DIV32K 2
17 #define CLK_RTC32K 3
18 #define CLK_WIFI_DIV 4
19 #define CLK_WIFI_OSC0 5
20 #define CLK_WIFI 6
21 #define CLK_PMU 7
22 #define SCLK_UART1_DIV 8
23 #define SCLK_UART1_FRACDIV 9
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H A Dqcom,gcc-sc8280xp.h8 #define _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H
11 #define GCC_GPLL0 0
12 #define GCC_GPLL0_OUT_EVEN 1
13 #define GCC_GPLL2 2
14 #define GCC_GPLL4 3
15 #define GCC_GPLL7 4
16 #define GCC_GPLL8 5
17 #define GCC_GPLL9 6
18 #define GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK 7
19 #define GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CL
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/freebsd/crypto/openssh/
H A Dssh_namespace.h5 #define Blowfish_decipher Fssh_Blowfish_decipher
6 #define Blowfish_encipher Fssh_Blowfish_encipher
7 #define Blowfish_expand0state Fssh_Blowfish_expand0state
8 #define Blowfish_expandstate Fssh_Blowfish_expandstate
9 #define Blowfish_initstate Fssh_Blowfish_initstate
10 #define Blowfish_stream2word Fssh_Blowfish_stream2word
11 #define Decode Fssh_Decode
12 #define EVP_CIPHER_CTX_get_iv Fssh_EVP_CIPHER_CTX_get_iv
13 #define EVP_CIPHER_CTX_set_iv Fssh_EVP_CIPHER_CTX_set_iv
14 #define Encode Fssh_Encode
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/freebsd/sys/contrib/device-tree/include/dt-bindings/mailbox/
H A Dmediatek,mt8188-gce.h7 #define _DT_BINDINGS_GCE_MT8188_H
9 #define CMDQ_THR_PRIO_LOWEST 0
10 #define CMDQ_THR_PRIO_1 1
11 #define CMDQ_THR_PRIO_2 2
12 #define CMDQ_THR_PRIO_3 3
13 #define CMDQ_THR_PRIO_4 4
14 #define CMDQ_THR_PRIO_5 5
15 #define CMDQ_THR_PRIO_6 6
16 #define CMDQ_THR_PRIO_HIGHEST 7
18 #define SUBSYS_1400XXXX 0
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/freebsd/crypto/openssl/include/openssl/
H A Dcryptoerr_legacy.h18 # define OPENSSL_CRYPTOERR_LEGACY_H
82 # define ASN1_F_A2D_ASN1_OBJECT 0
83 # define ASN1_F_A2I_ASN1_INTEGER 0
84 # define ASN1_F_A2I_ASN1_STRING 0
85 # define ASN1_F_APPEND_EXP 0
86 # define ASN1_F_ASN1_BIO_INIT 0
87 # define ASN1_F_ASN1_BIT_STRING_SET_BIT 0
88 # define ASN1_F_ASN1_CB 0
89 # define ASN1_F_ASN1_CHECK_TLEN 0
90 # define ASN1_F_ASN1_COLLECT 0
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H A Dobj_mac.h13 # define OPENSSL_OBJ_MAC_H
16 #define SN_undef "UNDEF"
17 #define LN_undef "undefined"
18 #define NID_undef 0
19 #define OBJ_undef 0L
21 #define SN_itu_t "ITU-T"
22 #define LN_itu_t "itu-t"
23 #define NID_itu_t 645
24 #define OBJ_itu_t 0L
26 #define NID_ccitt 404
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/freebsd/sys/contrib/device-tree/include/dt-bindings/gce/
H A Dmt8195-gce.h8 #define _DT_BINDINGS_GCE_MT8195_H
11 #define CMDQ_NO_TIMEOUT 0xffffffff
12 #define CMDQ_TIMEOUT_DEFAULT 1000
15 #define CMDQ_THR_PRIO_LOWEST 0
16 #define CMDQ_THR_PRIO_1 1
17 #define CMDQ_THR_PRIO_2 2
18 #define CMDQ_THR_PRIO_3 3
19 #define CMDQ_THR_PRIO_4 4
20 #define CMDQ_THR_PRIO_5 5
21 #define CMDQ_THR_PRIO_6 6
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/freebsd/sys/contrib/device-tree/include/dt-bindings/pinctrl/
H A Dpads-imx8qm.h8 #define _IMX8QM_PADS_H
11 #define IMX8QM_SIM0_CLK 0
12 #define IMX8QM_SIM0_RST 1
13 #define IMX8QM_SIM0_IO 2
14 #define IMX8QM_SIM0_PD 3
15 #define IMX8QM_SIM0_POWER_EN 4
16 #define IMX8QM_SIM0_GPIO0_00 5
17 #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_SIM 6
18 #define IMX8QM_M40_I2C0_SCL 7
19 #define IMX8QM_M40_I2C0_SDA 8
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H A Dpads-imx8qxp.h8 #define _IMX8QXP_PADS_H
11 #define IMX8QXP_PCIE_CTRL0_PERST_B 0
12 #define IMX8QXP_PCIE_CTRL0_CLKREQ_B 1
13 #define IMX8QXP_PCIE_CTRL0_WAKE_B 2
14 #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
15 #define IMX8QXP_USB_SS3_TC0 4
16 #define IMX8QXP_USB_SS3_TC1 5
17 #define IMX8QXP_USB_SS3_TC2 6
18 #define IMX8QXP_USB_SS3_TC3 7
19 #define IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO 8
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H A Dpads-imx8dxl.h7 #define _IMX8DXL_PADS_H
10 #define IMX8DXL_PCIE_CTRL0_PERST_B 0
11 #define IMX8DXL_PCIE_CTRL0_CLKREQ_B 1
12 #define IMX8DXL_PCIE_CTRL0_WAKE_B 2
13 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
14 #define IMX8DXL_USB_SS3_TC0 4
15 #define IMX8DXL_USB_SS3_TC1 5
16 #define IMX8DXL_USB_SS3_TC2 6
17 #define IMX8DXL_USB_SS3_TC3 7
18 #define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 8
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/freebsd/sys/contrib/device-tree/include/dt-bindings/reset/
H A Drockchip,rk3588-cru.h11 #define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
13 #define SRST_A_TOP_BIU 0
14 #define SRST_P_TOP_BIU 1
15 #define SRST_P_CSIPHY0 2
16 #define SRST_CSIPHY0 3
17 #define SRST_P_CSIPHY1 4
18 #define SRST_CSIPHY1 5
19 #define SRST_A_TOP_M500_BIU 6
21 #define SRST_A_TOP_M400_BIU 7
22 #define SRST_A_TOP_S200_BIU 8
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H A Drockchip,rk3576-cru.h11 #define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H
13 #define SRST_A_TOP_BIU 0
14 #define SRST_P_TOP_BIU 1
15 #define SRST_A_TOP_MID_BIU 2
16 #define SRST_A_SECURE_HIGH_BIU 3
17 #define SRST_H_TOP_BIU 4
19 #define SRST_H_VO0VOP_CHANNEL_BIU 5
20 #define SRST_A_VO0VOP_CHANNEL_BIU 6
22 #define SRST_BISRINTF 7
24 #define SRST_H_AUDIO_BIU 8
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/freebsd/sys/contrib/device-tree/include/dt-bindings/firmware/imx/
H A Drsrc.h8 #define __DT_BINDINGS_RSCRC_IMX_H
16 #define IMX_SC_R_AP_0 0
17 #define IMX_SC_R_AP_0_0 1
18 #define IMX_SC_R_AP_0_1 2
19 #define IMX_SC_R_AP_0_2 3
20 #define IMX_SC_R_AP_0_3 4
21 #define IMX_SC_R_AP_1 5
22 #define IMX_SC_R_AP_1_0 6
23 #define IMX_SC_R_AP_1_1 7
24 #define IMX_SC_R_AP_1_2 8
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/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_radio_2056.h30 #define __IF_BWN_RADIO_2056_H__
32 #define B2056_SYN (0x0 << 12)
33 #define B2056_TX0 (0x2 << 12)
34 #define B2056_TX1 (0x3 << 12)
35 #define B2056_RX0 (0x6 << 12)
36 #define B2056_RX1 (0x7 << 12)
37 #define B2056_ALLTX (0xE << 12)
38 #define B2056_ALLRX (0xF << 12)
40 #define B2056_SYN_RESERVED_ADDR0 0x00
41 #define B2056_SYN_IDCODE 0x01
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/freebsd/sys/dev/dialog/da9063/
H A Dda9063reg.h29 #define _DA9063_REG_H_
39 #define DA9063_PAGE_CON 0x00
40 #define DA9063_PAGE_CON_REG_PAGE_SHIFT 0
41 #define DA9063_PAGE_CON_REG_PAGE_MASK 0x07
42 #define DA9063_PAGE_CON_WRITE_MODE 0x40
43 #define DA9063_PAGE_CON_REVERT 0x80
47 #define DA9063_STATUS_A 0x01
48 #define DA9063_STATUS_A_NONKEY 0x01
49 #define DA9063_STATUS_A_WAKE 0x02
50 #define DA9063_STATUS_A_DVC_BUSY 0x04
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