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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-fm-rx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _fm-rx-controls:
13 .. _fm-rx-control-id:
27 Gets RDS Programme Type field. This encodes up to 31 pre-defined
45 wishes to transmit longer PS names, programme-related information or
70 enum v4l2_deemphasis -
71 Configures the de-emphasis value for reception. A de-emphasis filter
75 values for de-emphasis. Here they are:
79 .. flat-table::
80 :header-rows: 0
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/linux/sound/soc/codecs/
H A Dpcm3008.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in pcm3008_dac_ev()
32 struct pcm3008_setup_data *setup = component->dev->platform_data; in pcm3008_dac_ev()
34 gpio_set_value_cansleep(setup->pdda_pin, in pcm3008_dac_ev()
44 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in pcm3008_adc_ev()
45 struct pcm3008_setup_data *setup = component->dev->platform_data; in pcm3008_adc_ev()
47 gpio_set_value_cansleep(setup->pdad_pin, in pcm3008_adc_ev()
80 .name = "pcm3008-hifi",
109 struct pcm3008_setup_data *setup = pdev->dev.platform_data; in pcm3008_codec_probe()
113 return -EINVAL; in pcm3008_codec_probe()
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H A Dak4619.c1 // SPDX-License-Identifier: GPL-2.0
3 * ak4619.c -- Asahi Kasei ALSA SoC Audio driver
47 #define DAC_DEMP 0x13 /* DAC De-Emphasis Setting */
126 /* DAC De-Emphasis Setting */
165 * min : 0xFE : -115.0 dB
168 static const DECLARE_TLV_DB_SCALE(dac_tlv, -11550, 50, 1);
175 * min: 0x00 : -6.0 dB
177 static const DECLARE_TLV_DB_SCALE(mic_tlv, -600, 300, 0);
184 * min : 0xFE : -103.0 dB
187 static const DECLARE_TLV_DB_SCALE(adc_tlv, -10350, 50, 1);
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H A Dad1836.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2009-2011 Analog Devices Inc.
38 * AD1836 volume/mute/de-emphasis etc. controls
99 /* ADC high-pass filter */
103 /* DAC de-emphasis */
141 return -EINVAL; in ad1836_set_dai_fmt()
148 return -EINVAL; in ad1836_set_dai_fmt()
156 return -EINVAL; in ad1836_set_dai_fmt()
166 struct ad1836_priv *ad1836 = snd_soc_component_get_drvdata(dai->component); in ad1836_hw_params()
182 return -EINVAL; in ad1836_hw_params()
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H A Dak4458.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <sound/soc-dapm.h>
84 * from -127 to 0 dB in 0.5 dB steps (mute instead of -127.5 dB)
86 static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
101 * 0, 0, 0 : Sharp Roll-Off Filter
102 * 0, 0, 1 : Slow Roll-Off Filter
103 * 0, 1, 0 : Short delay Sharp Roll-Off Filter
104 * 0, 1, 1 : Short delay Slow Roll-Off Filter
105 * 1, *, * : Super Slow Roll-Off Filter
108 "Sharp Roll-Off Filter",
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H A Dad193x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 * AD193X volume/mute/de-emphasis etc. controls
37 static const DECLARE_TLV_DB_MINMAX(adau193x_tlv, -9563, 0);
67 /* DAC de-emphasis */
78 /* ADC high-pass filter */
105 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in ad193x_check_pll()
108 return !!ad193x->sysclk; in ad193x_check_pll()
131 switch (ad193x->type) { in ad193x_has_adc()
148 struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(dai->component); in ad193x_mute()
151 regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL2, in ad193x_mute()
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H A Dpcm1681.c1 // SPDX-License-Identifier: GPL-2.0-or-later
37 #define PCM1681_DEEMPH_CONTROL 0x0a /* De-emphasis control */
85 int i, val = -1, enable = 0; in pcm1681_set_deemph()
87 if (priv->deemph) { in pcm1681_set_deemph()
89 if (pcm1681_deemph[i] == priv->rate) { in pcm1681_set_deemph()
96 if (val != -1) { in pcm1681_set_deemph()
97 regmap_update_bits(priv->regmap, PCM1681_DEEMPH_CONTROL, in pcm1681_set_deemph()
105 return regmap_update_bits(priv->regmap, PCM1681_DEEMPH_CONTROL, in pcm1681_set_deemph()
115 ucontrol->value.integer.value[0] = priv->deemph; in pcm1681_get_deemph()
126 priv->deemph = ucontrol->value.integer.value[0]; in pcm1681_put_deemph()
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H A Dcs4271.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * The data format accepted is I2S or left-justified.
130 * Default CS4271 power-up configuration
131 * Array contains non-existing in hw register at address 0
159 /* Current sample rate for de-emphasis control */
173 SND_SOC_DAPM_OUTPUT("AOUTA-"),
175 SND_SOC_DAPM_OUTPUT("AOUTB-"),
183 { "AOUTA-", NULL, "Playback" },
185 { "AOUTB-", NULL, "Playback" },
196 struct snd_soc_component *component = codec_dai->component; in cs4271_set_dai_sysclk()
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H A Dcs4349.h1 /* SPDX-License-Identifier: GPL-2.0-only */
42 /* (Digital Interface Format, De-Emphasis Control, Functional Mode */
H A Dssm2602.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
81 #define APDIGI_DE_EMPHASIS 0x006 /* De-Emphasis Control …
107 #define SRATE_BOS_RATE 0x002 /* Base Over-Sampling rate …
H A Dcs42xx8.c52 /* -127.5dB to 0dB with step of 0.5dB */
53 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
54 /* -64dB to 24dB with step of 0.5dB */
55 static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 0);
57 static const char *const cs42xx8_adc_single[] = { "Differential", "Single-Ended" };
82 CS42XX8_VOLAIN2, 0, -0x80, 0x30, 7, 0, adc_tlv),
84 CS42XX8_VOLAIN4, 0, -0x80, 0x30, 7, 0, adc_tlv),
91 SOC_SINGLE("ADC High-Pass Filter Switch", CS42XX8_ADCCTL, 7, 1, 1),
92 SOC_SINGLE("DAC De-emphasis Switch", CS42XX8_ADCCTL, 5, 1, 0),
105 CS42XX8_VOLAIN6, 0, -0x80, 0x30, 7, 0, adc_tlv),
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/linux/Documentation/devicetree/bindings/pci/
H A Dfsl,imx6q-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
22 clock-names:
26 num-lanes:
29 fsl,imx7d-pcie-phy:
31 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
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/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
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H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Jun <jun.li@nxp.com>
15 - enum:
16 - fsl,imx8mq-usb-phy
17 - fsl,imx8mp-usb-phy
18 - items:
19 - const: fsl,imx95-usb-phy
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/linux/Documentation/devicetree/bindings/sound/
H A Duda1334.txt7 - compatible : "nxp,uda1334"
8 - nxp,mute-gpios: a GPIO spec for the MUTE pin.
9 - nxp,deemph-gpios: a GPIO spec for the De-emphasis pin
13 uda1334: audio-codec {
15 nxp,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
16 nxp,deemph-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
/linux/drivers/media/radio/wl128x/
H A Dfmdrv_common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
129 #define fm_cb(skb) ((struct fm_skb_cb *)(skb->cb))
131 /* FM Channel-8 command message format */
133 __u8 hdr; /* Logical Channel-8 */
142 /* FM Channel-8 event messgage format */
144 __u8 header; /* Logical Channel-8 */
223 #define FM_RX_RSSI_THRESHOLD_MIN -128
231 /* FM RX De-emphasis filter modes */
347 /* FM TX Pre-emphasis filter values */
357 /* Functions exported by FM common sub-module */
H A Dfmdrv_rx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * This sub-module of FM driver implements FM RX functionality.
17 fmdev->rx.rds.flag = FM_RDS_DISABLE; in fm_rx_reset_rds_cache()
18 fmdev->rx.rds.last_blk_idx = 0; in fm_rx_reset_rds_cache()
19 fmdev->rx.rds.wr_idx = 0; in fm_rx_reset_rds_cache()
20 fmdev->rx.rds.rd_idx = 0; in fm_rx_reset_rds_cache()
22 if (fmdev->rx.af_mode == FM_RX_RDS_AF_SWITCH_MODE_ON) in fm_rx_reset_rds_cache()
23 fmdev->irq_info.mask |= FM_LEV_EVENT; in fm_rx_reset_rds_cache()
28 fmdev->rx.stat_info.picode = FM_NO_PI_CODE; in fm_rx_reset_station_info()
29 fmdev->rx.stat_info.afcache_size = 0; in fm_rx_reset_station_info()
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/linux/Documentation/devicetree/bindings/scsi/
H A Dhisilicon-sas.txt6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
18 - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
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/linux/drivers/usb/dwc3/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * core.h - DesignWare USB3 DRD Core Header
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
20 #include <linux/dma-mapping.h>
37 * DWC3 Multiport controllers support up to 15 High-Speed PHYs
197 /* Global SoC Bus Configuration Register: AHB-prot/AXI-cache/OCP-ReqInfo */
683 * struct dwc3_event_buffer - Software event buffer representation
717 * struct dwc3_ep - device side endpoint representation
730 * @number: endpoint number (1 - 15)
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/linux/drivers/media/radio/si470x/
H A Dradio-si470x-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/media/radio/si470x/radio-si470x-common.c
8 * Copyright (c) 2012 Hans de Goede <hdegoede@redhat.com>
14 * 2008-01-12 Tobias Lorenz <tobias.lorenz@gmx.net>
16 * - First working version
17 * 2008-01-13 Tobias Lorenz <tobias.lorenz@gmx.net>
19 * - Improved error handling, every function now returns errno
20 * - Improved multi user access (start/mute/stop)
21 * - Channel doesn't get lost anymore after start/mute/stop
22 * - RDS support added (polling mode via interrupt EP 1)
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/linux/sound/i2c/other/
H A Dak4xxx-adda.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2000-2004 Jaroslav Kysela <perex@perex.cz>,
7 * Takashi Iwai <tiwai@suse.de>
18 #include <sound/ak4xxx-adda.h>
21 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.de>");
29 ak->ops.lock(ak, chip); in snd_akm4xxx_write()
30 ak->ops.write(ak, chip, reg, val); in snd_akm4xxx_write()
34 ak->ops.unlock(ak, chip); in snd_akm4xxx_write()
45 for (chip = 0; chip < ak->num_dacs/2; chip++) { in ak4524_reset()
50 for (reg = 0x04; reg < ak->total_regs; reg++) in ak4524_reset()
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/linux/drivers/phy/lantiq/
H A Dphy-lantiq-rcu-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
21 /* Transmitter HS Pre-Emphasis Enable */
69 .compatible = "lantiq,ase-usb2-phy",
73 .compatible = "lantiq,danube-usb2-phy",
77 .compatible = "lantiq,xrx100-usb2-phy",
81 .compatible = "lantiq,xrx200-usb2-phy",
85 .compatible = "lantiq,xrx300-usb2-phy",
96 if (priv->reg_bits->have_ana_cfg) { in ltq_rcu_usb2_phy_init()
97 regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset, in ltq_rcu_usb2_phy_init()
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-pcie2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
7 #include <linux/clk-provider.h>
16 #include <dt-bindings/phy/phy.h>
55 ret = reset_control_deassert(qphy->phy_reset); in qcom_pcie2_phy_init()
57 dev_err(qphy->dev, "cannot deassert pipe reset\n"); in qcom_pcie2_phy_init()
61 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qcom_pcie2_phy_init()
63 reset_control_assert(qphy->phy_reset); in qcom_pcie2_phy_init()
75 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
77 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
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H A Dphy-qcom-snps-femto-v2.c1 // SPDX-License-Identifier: GPL-2.0
82 "vdda-pll", "vdda33", "vdda18",
110 * struct qcom_snps_hsphy - snps hs phy attributes
143 struct device *dev = hsphy->dev; in qcom_snps_hsphy_clk_init()
145 hsphy->num_clks = 2; in qcom_snps_hsphy_clk_init()
146 hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL); in qcom_snps_hsphy_clk_init()
147 if (!hsphy->clks) in qcom_snps_hsphy_clk_init()
148 return -ENOMEM; in qcom_snps_hsphy_clk_init()
154 hsphy->clks[0].id = "cfg_ahb"; in qcom_snps_hsphy_clk_init()
155 hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb"); in qcom_snps_hsphy_clk_init()
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8m-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
79 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on()
80 switch (imx8_phy->drvdata->variant) { in imx8_pcie_phy_power_on()
82 reset_control_assert(imx8_phy->reset); in imx8_pcie_phy_power_on()
84 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ in imx8_pcie_phy_power_on()
85 if (imx8_phy->tx_deemph_gen1) in imx8_pcie_phy_power_on()
86 writel(imx8_phy->tx_deemph_gen1, in imx8_pcie_phy_power_on()
87 imx8_phy->base + PCIE_PHY_TRSV_REG5); in imx8_pcie_phy_power_on()
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