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/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
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H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Jun <jun.li@nxp.com>
15 - enum:
16 - fsl,imx8mq-usb-phy
17 - fsl,imx8mp-usb-phy
18 - items:
19 - const: fsl,imx95-usb-phy
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/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
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/linux/sound/soc/codecs/
H A Dak4619.c1 // SPDX-License-Identifier: GPL-2.0
3 * ak4619.c -- Asahi Kasei ALSA SoC Audio driver
47 #define DAC_DEMP 0x13 /* DAC De-Emphasis Setting */
126 /* DAC De-Emphasis Setting */
165 * min : 0xFE : -115.0 dB
168 static const DECLARE_TLV_DB_SCALE(dac_tlv, -11550, 50, 1);
175 * min: 0x00 : -6.0 dB
177 static const DECLARE_TLV_DB_SCALE(mic_tlv, -600, 300, 0);
184 * min : 0xFE : -103.0 dB
187 static const DECLARE_TLV_DB_SCALE(adc_tlv, -10350, 50, 1);
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H A Dak4458.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <sound/soc-dapm.h>
84 * from -127 to 0 dB in 0.5 dB steps (mute instead of -127.5 dB)
86 static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
101 * 0, 0, 0 : Sharp Roll-Off Filter
102 * 0, 0, 1 : Slow Roll-Off Filter
103 * 0, 1, 0 : Short delay Sharp Roll-Off Filter
104 * 0, 1, 1 : Short delay Slow Roll-Off Filter
105 * 1, *, * : Super Slow Roll-Off Filter
108 "Sharp Roll-Off Filter",
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H A Dad1836.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2009-2011 Analog Devices Inc.
38 * AD1836 volume/mute/de-emphasis etc. controls
99 /* ADC high-pass filter */
103 /* DAC de-emphasis */
141 return -EINVAL; in ad1836_set_dai_fmt()
148 return -EINVAL; in ad1836_set_dai_fmt()
156 return -EINVAL; in ad1836_set_dai_fmt()
166 struct ad1836_priv *ad1836 = snd_soc_component_get_drvdata(dai->component); in ad1836_hw_params()
182 return -EINVAL; in ad1836_hw_params()
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H A Dad193x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 * AD193X volume/mute/de-emphasis etc. controls
37 static const DECLARE_TLV_DB_MINMAX(adau193x_tlv, -9563, 0);
67 /* DAC de-emphasis */
78 /* ADC high-pass filter */
105 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in ad193x_check_pll()
108 return !!ad193x->sysclk; in ad193x_check_pll()
131 switch (ad193x->type) { in ad193x_has_adc()
148 struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(dai->component); in ad193x_mute()
151 regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL2, in ad193x_mute()
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H A Dcs4349.h1 /* SPDX-License-Identifier: GPL-2.0-only */
42 /* (Digital Interface Format, De-Emphasis Control, Functional Mode */
H A Dssm2602.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
81 #define APDIGI_DE_EMPHASIS 0x006 /* De-Emphasis Control …
107 #define SRATE_BOS_RATE 0x002 /* Base Over-Sampling rate …
H A Dcs42xx8.h2 * cs42xx8.h - Cirrus Logic CS42448/CS42888 Audio CODEC driver header file
58 #define CS42XX8_NUMREGS (CS42XX8_LASTREG - CS42XX8_FIRSTREG + 1)
94 #define CS42XX8_FUNCMOD_DAC_FM_MASK (((1 << CS42XX8_FUNCMOD_DAC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_…
98 #define CS42XX8_FUNCMOD_ADC_FM_MASK (((1 << CS42XX8_FUNCMOD_ADC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_…
104 #define CS42XX8_FUNCMOD_MFREQ_MASK (((1 << CS42XX8_FUNCMOD_MFREQ_WIDTH) - 1) << CS42XX8_FUNCMOD_MF…
125 #define CS42XX8_INTF_DAC_DIF_MASK (((1 << CS42XX8_INTF_DAC_DIF_WIDTH) - 1) << CS42XX8_INTF_DAC_DIF…
135 #define CS42XX8_INTF_ADC_DIF_MASK (((1 << CS42XX8_INTF_ADC_DIF_WIDTH) - 1) << CS42XX8_INTF_ADC_DIF…
144 /* ADC Control & DAC De-Emphasis (Address 05h) */
173 #define CS42XX8_TXCTL_DAC_SZC_MASK (((1 << CS42XX8_TXCTL_DAC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_DAC_…
188 #define CS42XX8_TXCTL_ADC_SZC_MASK (((1 << CS42XX8_TXCTL_ADC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_ADC_…
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H A Dtas5086.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
70 #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
88 * Default TAS5086 power-up configuration
172 size = tas5086_register_size(&client->dev, reg); in tas5086_reg_write()
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H A Dadav80x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Lars-Peter Clausen <lars@metafoo.de>
113 #define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x))
214 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in adav80x_dapm_sysclk_check()
218 switch (adav80x->clk_src) { in adav80x_dapm_sysclk_check()
238 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in adav80x_dapm_pll_check()
241 return adav80x->pll_src == ADAV80X_PLL_SRC_XTAL; in adav80x_dapm_pll_check()
288 if (adav80x->deemph) { in adav80x_set_deemph()
289 switch (adav80x->rate) { in adav80x_set_deemph()
310 return regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2, in adav80x_set_deemph()
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H A Dssm2518.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
141 static const DECLARE_TLV_DB_MINMAX_MUTE(ssm2518_vol_tlv, -7125, 2400);
142 static const DECLARE_TLV_DB_SCALE(ssm2518_compressor_tlv, -3400, 200, 0);
143 static const DECLARE_TLV_DB_SCALE(ssm2518_expander_tlv, -8100, 300, 0);
144 static const DECLARE_TLV_DB_SCALE(ssm2518_noise_gate_tlv, -9600, 300, 0);
145 static const DECLARE_TLV_DB_SCALE(ssm2518_post_drc_tlv, -2400, 300, 0);
148 0, 7, TLV_DB_SCALE_ITEM(-2200, 200, 0),
149 7, 15, TLV_DB_SCALE_ITEM(-800, 100, 0),
186 SOC_SINGLE("Playback De-emphasis Switch", SSM2518_REG_MUTE_CTRL,
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/linux/Documentation/devicetree/bindings/sound/
H A Duda1334.txt7 - compatible : "nxp,uda1334"
8 - nxp,mute-gpios: a GPIO spec for the MUTE pin.
9 - nxp,deemph-gpios: a GPIO spec for the De-emphasis pin
13 uda1334: audio-codec {
15 nxp,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
16 nxp,deemph-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
/linux/Documentation/devicetree/bindings/scsi/
H A Dhisilicon-sas.txt6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
18 - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
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/linux/drivers/media/radio/si470x/
H A Dradio-si470x-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/media/radio/si470x/radio-si470x-common.c
8 * Copyright (c) 2012 Hans de Goede <hdegoede@redhat.com>
14 * 2008-01-12 Tobias Lorenz <tobias.lorenz@gmx.net>
16 * - First working version
17 * 2008-01-13 Tobias Lorenz <tobias.lorenz@gmx.net>
19 * - Improved error handling, every function now returns errno
20 * - Improved multi user access (start/mute/stop)
21 * - Channel doesn't get lost anymore after start/mute/stop
22 * - RDS support added (polling mode via interrupt EP 1)
[all …]
H A Dradio-si470x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * drivers/media/radio/si470x/radio-si470x.h
12 #define DRIVER_NAME "radio-si470x"
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ioctl.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-event.h>
28 #include <media/v4l2-device.h>
68 #define SYSCONFIG1_DE 0x0800 /* bits 11..11: De-emphasis (0=75us 1=50us) */
90 #define TEST1_AHIZEN 0x4000 /* bits 14..14: Audio High-Z Enable */
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/linux/sound/i2c/other/
H A Dak4xxx-adda.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2000-2004 Jaroslav Kysela <perex@perex.cz>,
7 * Takashi Iwai <tiwai@suse.de>
18 #include <sound/ak4xxx-adda.h>
21 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.de>");
29 ak->ops.lock(ak, chip); in snd_akm4xxx_write()
30 ak->ops.write(ak, chip, reg, val); in snd_akm4xxx_write()
34 ak->ops.unlock(ak, chip); in snd_akm4xxx_write()
45 for (chip = 0; chip < ak->num_dacs/2; chip++) { in ak4524_reset()
50 for (reg = 0x04; reg < ak->total_regs; reg++) in ak4524_reset()
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/linux/drivers/phy/lantiq/
H A Dphy-lantiq-rcu-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
21 /* Transmitter HS Pre-Emphasis Enable */
69 .compatible = "lantiq,ase-usb2-phy",
73 .compatible = "lantiq,danube-usb2-phy",
77 .compatible = "lantiq,xrx100-usb2-phy",
81 .compatible = "lantiq,xrx200-usb2-phy",
85 .compatible = "lantiq,xrx300-usb2-phy",
96 if (priv->reg_bits->have_ana_cfg) { in ltq_rcu_usb2_phy_init()
97 regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset, in ltq_rcu_usb2_phy_init()
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-pcie2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
7 #include <linux/clk-provider.h>
16 #include <dt-bindings/phy/phy.h>
55 ret = reset_control_deassert(qphy->phy_reset); in qcom_pcie2_phy_init()
57 dev_err(qphy->dev, "cannot deassert pipe reset\n"); in qcom_pcie2_phy_init()
61 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qcom_pcie2_phy_init()
63 reset_control_assert(qphy->phy_reset); in qcom_pcie2_phy_init()
75 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
77 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
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H A Dphy-qcom-snps-femto-v2.c1 // SPDX-License-Identifier: GPL-2.0
82 "vdda-pll", "vdda33", "vdda18",
110 * struct qcom_snps_hsphy - snps hs phy attributes
143 struct device *dev = hsphy->dev; in qcom_snps_hsphy_clk_init()
145 hsphy->num_clks = 2; in qcom_snps_hsphy_clk_init()
146 hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL); in qcom_snps_hsphy_clk_init()
147 if (!hsphy->clks) in qcom_snps_hsphy_clk_init()
148 return -ENOMEM; in qcom_snps_hsphy_clk_init()
154 hsphy->clks[0].id = "cfg_ahb"; in qcom_snps_hsphy_clk_init()
155 hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb"); in qcom_snps_hsphy_clk_init()
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8m-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
79 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on()
80 switch (imx8_phy->drvdata->variant) { in imx8_pcie_phy_power_on()
82 reset_control_assert(imx8_phy->reset); in imx8_pcie_phy_power_on()
84 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ in imx8_pcie_phy_power_on()
85 if (imx8_phy->tx_deemph_gen1) in imx8_pcie_phy_power_on()
86 writel(imx8_phy->tx_deemph_gen1, in imx8_pcie_phy_power_on()
87 imx8_phy->base + PCIE_PHY_TRSV_REG5); in imx8_pcie_phy_power_on()
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/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
198 * struct xpsgtr_phy - representation of a lane
219 * struct xpsgtr_dev - representation of a ZynMP GT device
271 return readl(gtr_dev->serdes + reg); in xpsgtr_read()
276 writel(value, gtr_dev->serdes + reg); in xpsgtr_write()
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/linux/drivers/block/drbd/
H A Ddrbd_protocol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
33 P_SUPERSEDED = 0x18, /* Used in proto C, two-primaries conflict detection */
74 P_ZEROES = 0x36, /* data sock: zero-out, WRITE_ZEROES */
154 u32 size; /* == bio->bi_size */
159 u32 size; /* == bio->bi_size */
166 * P_SUPERSEDED (proto C, two-primaries conflict detection)
196 /* Detect all-zeros during resync, and rather TRIM/UNMAP/DISCARD those blocks
203 * - indicates support for 128 MiB "batch bios",
206 * - indicates that we exchange additional settings in p_sizes
215 * back to zero-out.
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/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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