Home
last modified time | relevance | path

Searched full:ddrpll (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/clk/zynq/
H A Dclkc.c51 armpll, ddrpll, iopll, enumerator
240 cpu_parents[2] = clk_output_name[ddrpll]; in zynq_clk_setup()
245 periph_parents[3] = clk_output_name[ddrpll]; in zynq_clk_setup()
266 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], in zynq_clk_setup()
325 clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, in zynq_clk_setup()
331 clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, in zynq_clk_setup()
338 clk_register_divider(NULL, "dci_div0", "ddrpll", 0, in zynq_clk_setup()
/linux/Documentation/devicetree/bindings/clock/
H A Dcalxeda.yaml59 ddrpll: ddrpll@108 {
H A Dzynq-7000.txt42 1: ddrpll
96 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
H A Dnuvoton,ma35d1-clk.yaml36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
H A Dkeystone-pll.txt2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
/linux/drivers/clk/nuvoton/
H A Dclk-ma35d1-pll.c235 case DDRPLL: in ma35d1_clk_pll_recalc_rate()
267 case DDRPLL: in ma35d1_clk_pll_round_rate()
347 if (id == CAPLL || id == DDRPLL) in ma35d1_reg_clk_pll()
H A Dclk-ma35d1.c68 { .fw_name = "ddrpll", },
344 { .fw_name = "ddrpll", },
504 hws[DDRPLL] = ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll", in ma35d1_clocks_probe()
551 hws[DDR0_GATE] = ma35d1_clk_gate(dev, "ddr0_gate", "ddrpll", in ma35d1_clocks_probe()
553 hws[DDR6_GATE] = ma35d1_clk_gate(dev, "ddr6_gate", "ddrpll", in ma35d1_clocks_probe()
897 hws[DDR_GATE] = ma35d1_clk_gate(dev, "ddr_gate", "ddrpll", in ma35d1_clocks_probe()
/linux/arch/arm/boot/dts/calxeda/
H A Decx-common.dtsi145 ddrpll: ddrpll { label
/linux/drivers/clk/sifive/
H A Dfu540-prci.h76 .name = "ddrpll",
H A Dfu740-prci.h92 .name = "ddrpll",
/linux/arch/arm64/boot/dts/nuvoton/
H A Dma35d1-iot-512m.dts42 <&clk DDRPLL>,
H A Dma35d1-som-256m.dts42 <&clk DDRPLL>,
/linux/include/dt-bindings/clock/
H A Dnuvoton,ma35d1-clk.h21 #define DDRPLL 10 macro
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi320 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",