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Searched full:ddrclk (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/clk/rockchip/
H A Dclk-ddr.c32 struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw); in rockchip_ddrclk_sip_set_rate() local
36 spin_lock_irqsave(ddrclk->lock, flags); in rockchip_ddrclk_sip_set_rate()
40 spin_unlock_irqrestore(ddrclk->lock, flags); in rockchip_ddrclk_sip_set_rate()
74 struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw); in rockchip_ddrclk_get_parent() local
77 val = readl(ddrclk->reg_base + in rockchip_ddrclk_get_parent()
78 ddrclk->mux_offset) >> ddrclk->mux_shift; in rockchip_ddrclk_get_parent()
79 val &= GENMASK(ddrclk->mux_width - 1, 0); in rockchip_ddrclk_get_parent()
99 struct rockchip_ddrclk *ddrclk; in rockchip_clk_register_ddrclk() local
103 ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL); in rockchip_clk_register_ddrclk()
104 if (!ddrclk) in rockchip_clk_register_ddrclk()
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/linux/drivers/media/platform/ti/omap3isp/
H A Dispcsiphy.c223 /* THS_TERM: Programmed value = ceil(12.5 ns/DDRClk period) - 1. */ in omap3isp_csiphy_config()
226 /* THS_SETTLE: Programmed value = ceil(90 ns/DDRClk period) + 3. */ in omap3isp_csiphy_config()
/linux/drivers/clk/mvebu/
H A Dkirkwood.c83 { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
262 "ddrclk",
H A Dmv98dx3236.c93 { .id = MV98DX3236_CPU_TO_DDR, .name = "ddrclk" },
H A Darmada-38x.c73 { .id = A380_CPU_TO_DDR, .name = "ddrclk" },
H A Ddove.c78 { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
H A Dorion.c18 { .id = 0, .name = "ddrclk", }
H A Darmada-375.c89 { .id = A375_CPU_TO_DDR, .name = "ddrclk" },
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood.dtsi22 clock-names = "cpu_clk", "ddrclk", "powersave";