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Searched full:ddrclk (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-core-clock.txt18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
72 output names ("tclk", "cpuclk", "l2clk", "ddrclk")
H A Dmarvell,mvebu-core-clock.yaml29 3 = ddrclk (DDR clock)
35 3 = ddrclk (DDR clock)
48 2 = ddrclk (DDR clock)
55 3 = ddrclk (DDR controller clock derived from CPU0 clock)
60 2 = ddrclk (DDR controller clock derived from CPU0 clock)
/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/
H A Dkirkwood.txt12 cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave",
14 between the "cpu_clk" and the "ddrclk".
26 clock-names = "cpu_clk", "ddrclk", "powersave";
/freebsd/sys/riscv/sifive/
H A Dsifive_prci.c178 PLL(FU540_PRCI_DDRCLK, "ddrclk", FU540_PRCI_DDRPLL_CFG0),
225 PLL(FU740_PRCI_DDRCLK, "ddrclk", FU740_PRCI_DDRPLL_CFG0),
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dkirkwood.dtsi22 clock-names = "cpu_clk", "ddrclk", "powersave";