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/freebsd/lib/libpmc/pmu-events/arch/arm64/hisilicon/hip08/
H A Duncore-ddrc.json5 "BriefDescription": "DDRC total write operations",
6 "PublicDescription": "DDRC total write operations",
7 "Unit": "hisi_sccl,ddrc"
12 "BriefDescription": "DDRC total read operations",
13 "PublicDescription": "DDRC total read operations",
14 "Unit": "hisi_sccl,ddrc"
19 "BriefDescription": "DDRC write commands",
20 "PublicDescription": "DDRC write commands",
21 "Unit": "hisi_sccl,ddrc"
26 "BriefDescription": "DDRC read commands",
[all …]
H A Duncore-hha.json48 "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
49 "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes",
55 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
56 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
62 … "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
63 … "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
69 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
70 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/fsl/
H A Dimx8m-ddrc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
20 The Linux driver for the DDRC doesn't even map registers (they're included
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
31 - const: fsl,imx8m-ddrc
36 Base address and size of DDRC CTL area.
37 This is not currently mapped by the imx8m-ddrc driver.
64 ddrc: memory-controller@3d400000 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dsynopsys,ddrc-ecc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
27 - snps,ddrc-3.80a
28 - xlnx,zynq-ddrc-a05
29 - xlnx,zynqmp-ddrc-2.40a
47 - snps,ddrc-3.80a
48 - xlnx,zynqmp-ddrc-2.40a
61 compatible = "xlnx,zynq-ddrc-a05";
71 compatible = "xlnx,zynqmp-ddrc-2.40a";
H A Dsnps,dw-umctl2-ddrc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
28 const: snps,ddrc-3.80a
30 const: snps,dw-umctl2-ddrc
32 const: xlnx,zynqmp-ddrc-2.40a
36 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
61 reference clock, DDRC core clock, Scrubber standalone clock
62 (synchronous to the DDRC clock).
96 compatible = "xlnx,zynqmp-ddrc-2.40a";
107 compatible = "snps,dw-umctl2-ddrc";
H A Dsynopsys.txt14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
18 Required properties for "xlnx,zynqmp-ddrc-2.40a":
23 compatible = "xlnx,zynq-ddrc-a05";
28 compatible = "xlnx,zynqmp-ddrc-2.40a";
H A Dxlnx,zynq-ddrc-a05.yaml4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
20 const: xlnx,zynq-ddrc-a05
34 compatible = "xlnx,zynq-ddrc-a05";
/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dfsl,imx8m-noc.yaml53 fsl,ddrc:
81 fsl,ddrc = <&ddrc>;
96 ddrc: memory-controller@3d400000 {
97 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
/freebsd/lib/libpmc/pmu-events/arch/test/test_soc/cpu/
H A Duncore.json5 "BriefDescription": "DDRC write commands",
6 "PublicDescription": "DDRC write commands",
7 "Unit": "hisi_sccl,ddrc"
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-evk.dts20 &ddrc {
H A Dimx8mn-ddr4-evk.dts32 &ddrc {
H A Dimx8mm-kontron-n801x-som.dtsi43 &ddrc {
H A Dimx8mm-kontron-sl.dtsi43 &ddrc {
H A Dimx8mq.dtsi1577 fsl,ddrc = <&ddrc>;
1865 ddrc: memory-controller@3d400000 { label
1866 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
H A Dimx8mn.dtsi1302 ddrc: memory-controller@3d400000 { label
1303 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
H A Dimx8mm-beacon-som.dtsi46 &ddrc {
H A Dimx8mm-innocomm-wb15.dtsi38 &ddrc {
H A Dimx8mn-beacon-som.dtsi54 &ddrc {
H A Dimx8mm-phycore-som.dtsi50 &ddrc {
H A Dimx8mm-var-som.dtsi49 &ddrc {
H A Dimx8mm-venice-gw700x.dtsi79 &ddrc {
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_n5x_socdk.dts30 compatible = "snps,ddrc-3.80a";
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra20-pinmux.yaml47 ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls,
H A Dnvidia,tegra20-pinmux.txt89 ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra20-trimslice.dts220 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",

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