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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dbrcm,brcmstb-memc-ddr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
16 - brcm,brcmstb-memc-ddr-rev-b.1.x
17 - brcm,brcmstb-memc-ddr-rev-b.2.0
18 - brcm,brcmstb-memc-ddr-rev-b.2.1
19 - brcm,brcmstb-memc-ddr-rev-b.2.2
20 - brcm,brcmstb-memc-ddr-rev-b.2.3
21 - brcm,brcmstb-memc-ddr-rev-b.2.5
22 - brcm,brcmstb-memc-ddr-rev-b.2.6
23 - brcm,brcmstb-memc-ddr-rev-b.2.7
24 - brcm,brcmstb-memc-ddr-rev-b.2.8
[all …]
H A Dqca,ath79-ddr-controller.yaml4 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
22 - const: qca,ar9132-ddr-controller
23 - const: qca,ar7240-ddr-controller
26 - qca,ar7100-ddr-controller
27 - qca,ar7240-ddr-controller
29 "#qca,ddr-wb-channel-cells":
41 - "#qca,ddr-wb-channel-cells"
[all …]
H A Dath79-ddr-controller.txt1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the AR7xxx and AR9xxx families provides an interface
4 to flush the FIFO between various devices and the DDR. This is mainly used
10 - compatible: has to be "qca,<soc-type>-ddr-controller",
11 "qca,[ar7100|ar7240]-ddr-controller" as fallback.
12 On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
13 fallback, otherwise "qca,ar7240-ddr-controller" should be used.
15 - #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
21 compatible = "qca,ar9132-ddr-controller",
22 "qca,ar7240-ddr-controller";
[all …]
H A Dcalxeda-ddr-ctrlr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
7 title: Calxeda DDR memory controller
10 The Calxeda DDR memory controller is initialised and programmed by the
20 - calxeda,hb-ddr-ctrl
21 - calxeda,ecx-2000-ddr-ctrl
39 compatible = "calxeda,hb-ddr-ctrl";
H A Dsynopsys.txt3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
16 - reg: Should contain DDR controller registers location and length.
H A Drockchip,rk3399-dmc.yaml20 Node to get DDR loading. Refer to
44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
51 For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
318 Defines the power-down idle disable frequency in Hz. When the DDR
324 Defines the self-refresh idle disable frequency in Hz. When the DDR
[all...]
/freebsd/lib/libpmc/pmu-events/arch/arm64/freescale/imx8mp/sys/
H A Dmetrics.json3 "BriefDescription": "bytes of all masters read from ddr",
11 "BriefDescription": "bytes of all masters write to ddr",
19 "BriefDescription": "bytes of a53 core read from ddr",
27 "BriefDescription": "bytes of a53 core write to ddr",
35 "BriefDescription": "bytes of supermix(m7) core read from ddr",
43 "BriefDescription": "bytes of supermix(m7) write to ddr",
51 "BriefDescription": "bytes of gpu 3d read from ddr",
59 "BriefDescription": "bytes of gpu 3d write to ddr",
67 "BriefDescription": "bytes of gpu 2d read from ddr",
75 "BriefDescription": "bytes of gpu 2d write to ddr",
[all …]
H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Dfsl-imx-ddr.yaml4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
7 title: Freescale(NXP) IMX8/9 DDR performance monitor
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
19 - fsl,imx8mm-ddr-pmu
20 - fsl,imx8mn-ddr-pmu
21 - fsl,imx8mp-ddr-pmu
22 - fsl,imx93-ddr-pmu
25 - fsl,imx8mm-ddr
[all...]
H A Damlogic,g12-ddr-pmu.yaml4 $id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
7 title: Amlogic G12 DDR performance monitor
13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
21 - amlogic,g12a-ddr-pmu
22 - amlogic,g12b-ddr-pmu
23 - amlogic,sm1-ddr-pmu
49 compatible = "amlogic,g12a-ddr-pmu";
H A Dfsl-imx-ddr.txt1 * Freescale(NXP) IMX8 DDR performance monitor
6 "fsl,imx8-ddr-pmu"
7 "fsl,imx8m-ddr-pmu"
8 "fsl,imx8mp-ddr-pmu"
17 ddr-pmu@5c020000 {
18 compatible = "fsl,imx8-ddr-pmu";
H A Dmarvell-cn10k-ddr.yaml4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
7 title: Marvell CN10K DDR performance monitor
16 - marvell,cn10k-ddr-pmu
34 compatible = "marvell,cn10k-ddr-pmu";
/freebsd/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,brcmstb.txt148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
173 "brcm,brcmstb-ddr-phy-v240.2"
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mips/brcm/
H A Dsoc.txt45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
75 memc-ddr@2000 {
79 ddr-phy@6000 {
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
95 - reg : the DDR PHY register range and length
99 ddr-phy@6000 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dqca,ath79-cpu-intc.txt3 On most SoC the IRQ controller need to flush the DDR FIFO before running
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
34 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
35 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
43 #qca,ddr-wb-channel-cells = <1>;
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm7445.dtsi239 memc-ddr@2000 {
240 compatible = "brcm,brcmstb-memc-ddr";
244 ddr-phy@6000 {
245 compatible = "brcm,brcmstb-ddr-phy-v240.1";
250 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
261 memc-ddr@2000 {
262 compatible = "brcm,brcmstb-memc-ddr";
266 ddr-phy@6000 {
267 compatible = "brcm,brcmstb-ddr-phy-v240.1";
272 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
[all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/freescale/imx8mn/sys/
H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/freebsd/lib/libpmc/pmu-events/arch/arm64/freescale/imx8mm/sys/
H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/freebsd/lib/libpmc/pmu-events/arch/arm64/freescale/imx8mq/sys/
H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/freebsd/sys/geom/part/
H A Dg_part_apm.c53 struct apm_ddr ddr; member
270 table->ddr.ddr_sig = APM_DDR_SIG; in g_part_apm_create()
271 table->ddr.ddr_blksize = pp->sectorsize; in g_part_apm_create()
272 table->ddr.ddr_blkcount = last + 1; in g_part_apm_create()
408 /* Check that there's a Driver Descriptor Record (DDR). */ in g_part_apm_probe()
413 /* Normal Apple DDR */ in g_part_apm_probe()
414 table->ddr.ddr_sig = be16dec(buf); in g_part_apm_probe()
415 table->ddr.ddr_blksize = be16dec(buf + 2); in g_part_apm_probe()
416 table->ddr.ddr_blkcount = be32dec(buf + 4); in g_part_apm_probe()
418 if (table->ddr.ddr_blksize != pp->sectorsize) in g_part_apm_probe()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Damlogic,meson8-ddr-clkc.yaml4 $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
7 title: Amlogic DDR Clock Controller
15 - amlogic,meson8-ddr-clkc
16 - amlogic,meson8b-ddr-clkc
43 compatible = "amlogic,meson8-ddr-clkc";
H A Dmvebu-core-clock.txt12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
/freebsd/lib/libpmc/pmu-events/arch/x86/knightslanding/
H A Dmemory.json11 … code reads and prefetch code read requests that accounts for responses from DDR (local and far)",
14 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",
77 …ble data and L1 prefetch data read requests that accounts for responses from DDR (local and far)",
80 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",
198 …"BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)…
201 "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",
264 … "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)",
267 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",
330 …Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)",
333 "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Drk3399_dmc.txt5 - devfreq-events: Node to get DDR loading, Refer to
21 It should be a DCF interrupt. When DDR DVFS finishes
26 Following properties relate to DDR timing:
28 - rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
65 When DDR frequency is less than DRAM_DLL_DISB_FREQ,
70 MHz (Mega Hz). When DDR frequency is less than
76 when the DDR frequency is less then ddr3_odt_dis_freq,
102 When DDR frequency is less then ddr3_odt_dis_freq,
128 MHz (Mega Hz). When the DDR frequency is less then
/freebsd/sys/contrib/device-tree/src/mips/qca/
H A Dar9132.dtsi28 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
52 compatible = "qca,ar9132-ddr-controller",
53 "qca,ar7240-ddr-controller";
56 #qca,ddr-wb-channel-cells = <1>;
98 clock-output-names = "cpu", "ddr", "ahb";

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