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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dmicrochip,mcp3911.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Marcus Folkesson <marcus.folkesson@gmail.com>
12 - Kent Gustavsson <nedo80@gmail.com>
21 - microchip,mcp3910
22 - microchip,mcp3911
23 - microchip,mcp3912
24 - microchip,mcp3913
25 - microchip,mcp3914
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/linux/include/sound/
H A Dcs35l56.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <sound/cs-amp-lib.h>
210 /* ASP HiZ modes */
224 #define CS35L56_MAIN_RENDER_USER_VOLUME_MIN -400
273 /* Additional margin for SYSTEM_RESET to control port ready on SPI */
322 cs35l56->spi_payload_bu in cs35l56_init_config_for_spi()
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/linux/drivers/iio/adc/
H A Dmcp3911.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Microchip MCP3911, Two-channel Analog Front End
141 reg = MCP3911_REG_READ(reg, adc->dev_addr); in mcp3911_read()
142 ret = spi_write_then_read(adc->spi, &reg, 1, val, len); in mcp3911_read()
147 *val >>= ((4 - len) * 8); in mcp3911_read()
148 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val, in mcp3911_read()
155 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg); in mcp3911_write()
157 val <<= (3 - len) * 8; in mcp3911_write()
159 val |= MCP3911_REG_WRITE(reg, adc->dev_addr); in mcp3911_write()
161 return spi_write(adc->spi, &val, len + 1); in mcp3911_write()
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/linux/drivers/media/i2c/
H A Dmax2175.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
30 #define mxm_dbg(ctx, fmt, arg...) dev_dbg(&ctx->client->dev, fmt, ## arg)
31 #define mxm_err(ctx, fmt, arg...) dev_err(&ctx->client->dev, fmt, ## arg)
264 struct v4l2_subdev sd; /* Sub-device */
273 struct v4l2_ctrl *hsls; /* High-side/Low-side polarity */
288 bool am_hiz; /* AM Hi-Z filter */
321 ret = regmap_read(ctx->regmap, idx, &regval); in max2175_read()
334 ret = regmap_write(ctx->regmap, idx, val); in max2175_write()
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/linux/arch/m68k/include/asm/
H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
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H A DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
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