1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27select: 28 properties: 29 compatible: 30 contains: 31 const: riscv 32 33properties: 34 riscv,isa: 35 description: 36 Identifies the specific RISC-V instruction set architecture 37 supported by the hart. These are documented in the RISC-V 38 User-Level ISA document, available from 39 https://riscv.org/specifications/ 40 41 Due to revisions of the ISA specification, some deviations 42 have arisen over time. 43 Notably, riscv,isa was defined prior to the creation of the 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 45 implies "zicntr_zicsr_zifencei_zihpm". 46 47 While the isa strings in ISA specification are case 48 insensitive, letters in the riscv,isa string must be all 49 lowercase. 50 $ref: /schemas/types.yaml#/definitions/string 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 52 deprecated: true 53 54 riscv,isa-base: 55 description: 56 The base ISA implemented by this hart, as described by the 20191213 57 version of the unprivileged ISA specification. 58 enum: 59 - rv32i 60 - rv64i 61 62 riscv,isa-extensions: 63 $ref: /schemas/types.yaml#/definitions/string-array 64 minItems: 1 65 description: Extensions supported by the hart. 66 items: 67 anyOf: 68 # single letter extensions, in canonical order 69 - const: i 70 description: | 71 The base integer instruction set, as ratified in the 20191213 72 version of the unprivileged ISA specification. 73 74 This does not include Chapter 10, "Counters", which was moved into 75 the Zicntr and Zihpm extensions after the ratification of the 76 20191213 version of the unprivileged specification. 77 78 - const: m 79 description: 80 The standard M extension for integer multiplication and division, as 81 ratified in the 20191213 version of the unprivileged ISA 82 specification. 83 84 - const: a 85 description: 86 The standard A extension for atomic instructions, as ratified in the 87 20191213 version of the unprivileged ISA specification. 88 89 - const: f 90 description: 91 The standard F extension for single-precision floating point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: d 96 description: 97 The standard D extension for double-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: q 102 description: 103 The standard Q extension for quad-precision floating-point, as 104 ratified in the 20191213 version of the unprivileged ISA 105 specification. 106 107 - const: c 108 description: 109 The standard C extension for compressed instructions, as ratified in 110 the 20191213 version of the unprivileged ISA specification. 111 112 - const: v 113 description: 114 The standard V extension for vector operations, as ratified 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 116 encoding") of the riscv-v-spec. 117 118 - const: h 119 description: 120 The standard H extension for hypervisors as ratified in the 20191213 121 version of the privileged ISA specification. 122 123 # multi-letter extensions, sorted alphanumerically 124 - const: smaia 125 description: | 126 The standard Smaia supervisor-level extension for the advanced 127 interrupt architecture for machine-mode-visible csr and behavioural 128 changes to interrupts as frozen at commit ccbddab ("Merge pull 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 130 131 - const: smmpm 132 description: | 133 The standard Smmpm extension for M-mode pointer masking as 134 ratified at commit d70011dde6c2 ("Update to ratified state") 135 of riscv-j-extension. 136 137 - const: smnpm 138 description: | 139 The standard Smnpm extension for next-mode pointer masking as 140 ratified at commit d70011dde6c2 ("Update to ratified state") 141 of riscv-j-extension. 142 143 - const: smstateen 144 description: | 145 The standard Smstateen extension for controlling access to CSRs 146 added by other RISC-V extensions in H/S/VS/U/VU modes and as 147 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 148 149 - const: ssaia 150 description: | 151 The standard Ssaia supervisor-level extension for the advanced 152 interrupt architecture for supervisor-mode-visible csr and 153 behavioural changes to interrupts as frozen at commit ccbddab 154 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 155 156 - const: sscofpmf 157 description: | 158 The standard Sscofpmf supervisor-level extension for count overflow 159 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 160 to manually trigger workflow. (#2)") of riscv-count-overflow. 161 162 - const: ssnpm 163 description: | 164 The standard Ssnpm extension for next-mode pointer masking as 165 ratified at commit d70011dde6c2 ("Update to ratified state") 166 of riscv-j-extension. 167 168 - const: sstc 169 description: | 170 The standard Sstc supervisor-level extension for time compare as 171 ratified at commit 3f9ed34 ("Add ability to manually trigger 172 workflow. (#2)") of riscv-time-compare. 173 174 - const: svade 175 description: | 176 The standard Svade supervisor-level extension for SW-managed PTE A/D 177 bit updates as ratified in the 20240213 version of the privileged 178 ISA specification. 179 180 Both Svade and Svadu extensions control the hardware behavior when 181 the PTE A/D bits need to be set. The default behavior for the four 182 possible combinations of these extensions in the device tree are: 183 1) Neither Svade nor Svadu present in DT => It is technically 184 unknown whether the platform uses Svade or Svadu. Supervisor 185 software should be prepared to handle either hardware updating 186 of the PTE A/D bits or page faults when they need updated. 187 2) Only Svade present in DT => Supervisor must assume Svade to be 188 always enabled. 189 3) Only Svadu present in DT => Supervisor must assume Svadu to be 190 always enabled. 191 4) Both Svade and Svadu present in DT => Supervisor must assume 192 Svadu turned-off at boot time. To use Svadu, supervisor must 193 explicitly enable it using the SBI FWFT extension. 194 195 - const: svadu 196 description: | 197 The standard Svadu supervisor-level extension for hardware updating 198 of PTE A/D bits as ratified in the 20240528 version of the 199 privileged ISA specification. Please refer to Svade dt-binding 200 description for more details. 201 202 - const: svinval 203 description: 204 The standard Svinval supervisor-level extension for fine-grained 205 address-translation cache invalidation as ratified in the 20191213 206 version of the privileged ISA specification. 207 208 - const: svnapot 209 description: 210 The standard Svnapot supervisor-level extensions for napot 211 translation contiguity as ratified in the 20191213 version of the 212 privileged ISA specification. 213 214 - const: svpbmt 215 description: 216 The standard Svpbmt supervisor-level extensions for page-based 217 memory types as ratified in the 20191213 version of the privileged 218 ISA specification. 219 220 - const: svrsw60t59b 221 description: 222 The Svrsw60t59b extension for providing two more bits[60:59] to 223 PTE/PMD entry as ratified at commit 28bde925e7a7 ("PTE Reserved 224 for SW bits 60:59") of riscv-non-isa/riscv-iommu. 225 226 - const: svvptc 227 description: 228 The standard Svvptc supervisor-level extension for 229 address-translation cache behaviour with respect to invalid entries 230 as ratified at commit 4a69197e5617 ("Update to ratified state") of 231 riscv-svvptc. 232 233 - const: zaamo 234 description: | 235 The standard Zaamo extension for atomic memory operations as 236 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 237 (#1304)") of the unprivileged ISA specification. 238 239 - const: zabha 240 description: | 241 The Zabha extension for Byte and Halfword Atomic Memory Operations 242 as ratified at commit 49f49c842ff9 ("Update to Rafified state") of 243 riscv-zabha. 244 245 - const: zacas 246 description: | 247 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 248 is supported as ratified at commit 5059e0ca641c ("update to 249 ratified") of the riscv-zacas. 250 251 - const: zalasr 252 description: | 253 The standard Zalasr extension for load-acquire/store-release as frozen 254 at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. 255 256 - const: zalrsc 257 description: | 258 The standard Zalrsc extension for load-reserved/store-conditional as 259 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 260 (#1304)") of the unprivileged ISA specification. 261 262 - const: zawrs 263 description: | 264 The Zawrs extension for entering a low-power state or for trapping 265 to a hypervisor while waiting on a store to a memory location, as 266 ratified in commit 98918c844281 ("Merge pull request #1217 from 267 riscv/zawrs") of riscv-isa-manual. 268 269 - const: zba 270 description: | 271 The standard Zba bit-manipulation extension for address generation 272 acceleration instructions as ratified at commit 6d33919 ("Merge pull 273 request #158 from hirooih/clmul-fix-loop-end-condition") of 274 riscv-bitmanip. 275 276 - const: zbb 277 description: | 278 The standard Zbb bit-manipulation extension for basic bit-manipulation 279 as ratified at commit 6d33919 ("Merge pull request #158 from 280 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 281 282 - const: zbc 283 description: | 284 The standard Zbc bit-manipulation extension for carry-less 285 multiplication as ratified at commit 6d33919 ("Merge pull request 286 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 287 288 - const: zbkb 289 description: 290 The standard Zbkb bitmanip instructions for cryptography as ratified 291 in version 1.0 of RISC-V Cryptography Extensions Volume I 292 specification. 293 294 - const: zbkc 295 description: 296 The standard Zbkc carry-less multiply instructions as ratified 297 in version 1.0 of RISC-V Cryptography Extensions Volume I 298 specification. 299 300 - const: zbkx 301 description: 302 The standard Zbkx crossbar permutation instructions as ratified 303 in version 1.0 of RISC-V Cryptography Extensions Volume I 304 specification. 305 306 - const: zbs 307 description: | 308 The standard Zbs bit-manipulation extension for single-bit 309 instructions as ratified at commit 6d33919 ("Merge pull request #158 310 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 311 312 - const: zca 313 description: | 314 The Zca extension part of Zc* standard extensions for code size 315 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 316 RV64 as it contains no instructions") of riscv-code-size-reduction, 317 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 318 of zc.adoc to src tree."). 319 320 - const: zcb 321 description: | 322 The Zcb extension part of Zc* standard extensions for code size 323 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 324 RV64 as it contains no instructions") of riscv-code-size-reduction, 325 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 326 of zc.adoc to src tree."). 327 328 - const: zcd 329 description: | 330 The Zcd extension part of Zc* standard extensions for code size 331 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 332 RV64 as it contains no instructions") of riscv-code-size-reduction, 333 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 334 of zc.adoc to src tree."). 335 336 - const: zcf 337 description: | 338 The Zcf extension part of Zc* standard extensions for code size 339 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 340 RV64 as it contains no instructions") of riscv-code-size-reduction, 341 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 342 of zc.adoc to src tree."). 343 344 - const: zcmop 345 description: 346 The standard Zcmop extension version 1.0, as ratified in commit 347 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. 348 349 - const: zfa 350 description: 351 The standard Zfa extension for additional floating point 352 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 353 riscv-isa-manual. 354 355 - const: zfbfmin 356 description: 357 The standard Zfbfmin extension which provides minimal support for 358 16-bit half-precision brain floating-point instructions, as ratified 359 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 360 361 - const: zfh 362 description: 363 The standard Zfh extension for 16-bit half-precision binary 364 floating-point instructions, as ratified in commit 64074bc ("Update 365 version numbers for Zfh/Zfinx") of riscv-isa-manual. 366 367 - const: zfhmin 368 description: 369 The standard Zfhmin extension which provides minimal support for 370 16-bit half-precision binary floating-point instructions, as ratified 371 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 372 riscv-isa-manual. 373 374 - const: ziccrse 375 description: 376 The standard Ziccrse extension which provides forward progress 377 guarantee on LR/SC sequences, as ratified in commit b1d806605f87 378 ("Updated to ratified state.") of the riscv profiles specification. 379 380 - const: zk 381 description: 382 The standard Zk Standard Scalar cryptography extension as ratified 383 in version 1.0 of RISC-V Cryptography Extensions Volume I 384 specification. 385 386 - const: zkn 387 description: 388 The standard Zkn NIST algorithm suite extensions as ratified in 389 version 1.0 of RISC-V Cryptography Extensions Volume I 390 specification. 391 392 - const: zknd 393 description: | 394 The standard Zknd for NIST suite: AES decryption instructions as 395 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 396 specification. 397 398 - const: zkne 399 description: | 400 The standard Zkne for NIST suite: AES encryption instructions as 401 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 402 specification. 403 404 - const: zknh 405 description: | 406 The standard Zknh for NIST suite: hash function instructions as 407 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 408 specification. 409 410 - const: zkr 411 description: 412 The standard Zkr entropy source extension as ratified in version 413 1.0 of RISC-V Cryptography Extensions Volume I specification. 414 This string being present means that the CSR associated to this 415 extension is accessible at the privilege level to which that 416 device-tree has been provided. 417 418 - const: zks 419 description: 420 The standard Zks ShangMi algorithm suite extensions as ratified in 421 version 1.0 of RISC-V Cryptography Extensions Volume I 422 specification. 423 424 - const: zksed 425 description: | 426 The standard Zksed for ShangMi suite: SM4 block cipher instructions 427 as ratified in version 1.0 of RISC-V Cryptography Extensions 428 Volume I specification. 429 430 - const: zksh 431 description: | 432 The standard Zksh for ShangMi suite: SM3 hash function instructions 433 as ratified in version 1.0 of RISC-V Cryptography Extensions 434 Volume I specification. 435 436 - const: zkt 437 description: 438 The standard Zkt for data independent execution latency as ratified 439 in version 1.0 of RISC-V Cryptography Extensions Volume I 440 specification. 441 442 - const: zicbom 443 description: 444 The standard Zicbom extension for base cache management operations as 445 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 446 447 - const: zicbop 448 description: 449 The standard Zicbop extension for cache-block prefetch instructions 450 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 451 riscv-CMOs. 452 453 - const: zicboz 454 description: 455 The standard Zicboz extension for cache-block zeroing as ratified 456 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 457 458 - const: zicntr 459 description: 460 The standard Zicntr extension for base counters and timers, as 461 ratified in the 20191213 version of the unprivileged ISA 462 specification. 463 464 - const: zicond 465 description: 466 The standard Zicond extension for conditional arithmetic and 467 conditional-select/move operations as ratified in commit 95cf1f9 468 ("Add changes requested by Ved during signoff") of riscv-zicond. 469 470 - const: zicsr 471 description: | 472 The standard Zicsr extension for control and status register 473 instructions, as ratified in the 20191213 version of the 474 unprivileged ISA specification. 475 476 This does not include Chapter 10, "Counters", which documents 477 special case read-only CSRs, that were moved into the Zicntr and 478 Zihpm extensions after the ratification of the 20191213 version of 479 the unprivileged specification. 480 481 - const: zifencei 482 description: 483 The standard Zifencei extension for instruction-fetch fence, as 484 ratified in the 20191213 version of the unprivileged ISA 485 specification. 486 487 - const: zihintpause 488 description: 489 The standard Zihintpause extension for pause hints, as ratified in 490 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 491 492 - const: zihintntl 493 description: 494 The standard Zihintntl extension for non-temporal locality hints, as 495 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 496 riscv-isa-manual. 497 498 - const: zihpm 499 description: 500 The standard Zihpm extension for hardware performance counters, as 501 ratified in the 20191213 version of the unprivileged ISA 502 specification. 503 504 - const: zimop 505 description: 506 The standard Zimop extension version 1.0, as ratified in commit 507 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. 508 509 - const: ztso 510 description: 511 The standard Ztso extension for total store ordering, as ratified 512 in commit 2e5236 ("Ztso is now ratified.") of the 513 riscv-isa-manual. 514 515 - const: zvbb 516 description: 517 The standard Zvbb extension for vectored basic bit-manipulation 518 instructions, as ratified in commit 56ed795 ("Update 519 riscv-crypto-spec-vector.adoc") of riscv-crypto. 520 521 - const: zvbc 522 description: 523 The standard Zvbc extension for vectored carryless multiplication 524 instructions, as ratified in commit 56ed795 ("Update 525 riscv-crypto-spec-vector.adoc") of riscv-crypto. 526 527 - const: zve32f 528 description: 529 The standard Zve32f extension for embedded processors, as ratified 530 in commit 6f702a2 ("Vector extensions are now ratified") of 531 riscv-v-spec. 532 533 - const: zve32x 534 description: 535 The standard Zve32x extension for embedded processors, as ratified 536 in commit 6f702a2 ("Vector extensions are now ratified") of 537 riscv-v-spec. 538 539 - const: zve64d 540 description: 541 The standard Zve64d extension for embedded processors, as ratified 542 in commit 6f702a2 ("Vector extensions are now ratified") of 543 riscv-v-spec. 544 545 - const: zve64f 546 description: 547 The standard Zve64f extension for embedded processors, as ratified 548 in commit 6f702a2 ("Vector extensions are now ratified") of 549 riscv-v-spec. 550 551 - const: zve64x 552 description: 553 The standard Zve64x extension for embedded processors, as ratified 554 in commit 6f702a2 ("Vector extensions are now ratified") of 555 riscv-v-spec. 556 557 - const: zvfbfmin 558 description: 559 The standard Zvfbfmin extension for minimal support for vectored 560 16-bit half-precision brain floating-point instructions, as ratified 561 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 562 563 - const: zvfbfwma 564 description: 565 The standard Zvfbfwma extension for vectored half-precision brain 566 floating-point widening multiply-accumulate instructions, as ratified 567 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 568 569 - const: zvfh 570 description: 571 The standard Zvfh extension for vectored half-precision 572 floating-point instructions, as ratified in commit e2ccd05 573 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 574 575 - const: zvfhmin 576 description: 577 The standard Zvfhmin extension for vectored minimal half-precision 578 floating-point instructions, as ratified in commit e2ccd05 579 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 580 581 - const: zvkb 582 description: 583 The standard Zvkb extension for vector cryptography bit-manipulation 584 instructions, as ratified in commit 56ed795 ("Update 585 riscv-crypto-spec-vector.adoc") of riscv-crypto. 586 587 - const: zvkg 588 description: 589 The standard Zvkg extension for vector GCM/GMAC instructions, as 590 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 591 of riscv-crypto. 592 593 - const: zvkn 594 description: 595 The standard Zvkn extension for NIST algorithm suite instructions, as 596 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 597 of riscv-crypto. 598 599 - const: zvknc 600 description: 601 The standard Zvknc extension for NIST algorithm suite with carryless 602 multiply instructions, as ratified in commit 56ed795 ("Update 603 riscv-crypto-spec-vector.adoc") of riscv-crypto. 604 605 - const: zvkned 606 description: 607 The standard Zvkned extension for Vector AES block cipher 608 instructions, as ratified in commit 56ed795 ("Update 609 riscv-crypto-spec-vector.adoc") of riscv-crypto. 610 611 - const: zvkng 612 description: 613 The standard Zvkng extension for NIST algorithm suite with GCM 614 instructions, as ratified in commit 56ed795 ("Update 615 riscv-crypto-spec-vector.adoc") of riscv-crypto. 616 617 - const: zvknha 618 description: | 619 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 620 hash (SHA-256 only) instructions, as ratified in commit 621 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 622 623 - const: zvknhb 624 description: | 625 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 626 hash (SHA-256 and SHA-512) instructions, as ratified in commit 627 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 628 629 - const: zvks 630 description: 631 The standard Zvks extension for ShangMi algorithm suite 632 instructions, as ratified in commit 56ed795 ("Update 633 riscv-crypto-spec-vector.adoc") of riscv-crypto. 634 635 - const: zvksc 636 description: 637 The standard Zvksc extension for ShangMi algorithm suite with 638 carryless multiplication instructions, as ratified in commit 56ed795 639 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 640 641 - const: zvksed 642 description: | 643 The standard Zvksed extension for ShangMi suite: SM4 block cipher 644 instructions, as ratified in commit 56ed795 ("Update 645 riscv-crypto-spec-vector.adoc") of riscv-crypto. 646 647 - const: zvksh 648 description: | 649 The standard Zvksh extension for ShangMi suite: SM3 secure hash 650 instructions, as ratified in commit 56ed795 ("Update 651 riscv-crypto-spec-vector.adoc") of riscv-crypto. 652 653 - const: zvksg 654 description: 655 The standard Zvksg extension for ShangMi algorithm suite with GCM 656 instructions, as ratified in commit 56ed795 ("Update 657 riscv-crypto-spec-vector.adoc") of riscv-crypto. 658 659 - const: zvkt 660 description: 661 The standard Zvkt extension for vector data-independent execution 662 latency, as ratified in commit 56ed795 ("Update 663 riscv-crypto-spec-vector.adoc") of riscv-crypto. 664 665 # vendor extensions, each extension sorted alphanumerically under the 666 # vendor they belong to. Vendors are sorted alphanumerically as well. 667 668 # Andes 669 - const: xandespmu 670 description: 671 The Andes Technology performance monitor extension for counter overflow 672 and privilege mode filtering. For more details, see Counter Related 673 Registers in the AX45MP datasheet. 674 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 675 676 # MIPS 677 - const: xmipsexectl 678 description: 679 The MIPS extension for execution control as documented in 680 https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf 681 682 # SiFive 683 - const: xsfcease 684 description: 685 SiFive CEASE Instruction Extensions Specification. 686 See more details in 687 https://www.sifive.com/document-file/freedom-u740-c000-manual 688 689 - const: xsfcflushdlone 690 description: 691 SiFive L1D Cache Flush Instruction Extensions Specification. 692 See more details in 693 https://www.sifive.com/document-file/freedom-u740-c000-manual 694 695 - const: xsfpgflushdlone 696 description: 697 SiFive PGFLUSH Instruction Extensions for the power management. The 698 CPU will flush the L1D and enter the cease state after executing 699 the instruction. 700 701 - const: xsfvqmaccdod 702 description: 703 SiFive Int8 Matrix Multiplication Extensions Specification. 704 See more details in 705 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 706 707 - const: xsfvqmaccqoq 708 description: 709 SiFive Int8 Matrix Multiplication Extensions Specification. 710 See more details in 711 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 712 713 - const: xsfvfnrclipxfqf 714 description: 715 SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. 716 See more details in 717 https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions 718 719 - const: xsfvfwmaccqqq 720 description: 721 SiFive Matrix Multiply Accumulate Instruction Extensions Specification. 722 See more details in 723 https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction 724 725 # T-HEAD 726 - const: xtheadvector 727 description: 728 The T-HEAD specific 0.7.1 vector implementation as written in 729 https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. 730 731 allOf: 732 - if: 733 contains: 734 const: d 735 then: 736 contains: 737 const: f 738 # Zcb depends on Zca 739 - if: 740 contains: 741 const: zcb 742 then: 743 contains: 744 const: zca 745 # Zcd depends on Zca and D 746 - if: 747 contains: 748 const: zcd 749 then: 750 allOf: 751 - contains: 752 const: zca 753 - contains: 754 const: d 755 # Zcf depends on Zca and F 756 - if: 757 contains: 758 const: zcf 759 then: 760 allOf: 761 - contains: 762 const: zca 763 - contains: 764 const: f 765 # Zcmop depends on Zca 766 - if: 767 contains: 768 const: zcmop 769 then: 770 contains: 771 const: zca 772 # Zfbfmin depends on F 773 - if: 774 contains: 775 const: zfbfmin 776 then: 777 contains: 778 const: f 779 # Zvfbfmin depends on V or Zve32f 780 - if: 781 contains: 782 const: zvfbfmin 783 then: 784 oneOf: 785 - contains: 786 const: v 787 - contains: 788 const: zve32f 789 # Zvfbfwma depends on Zfbfmin and Zvfbfmin 790 - if: 791 contains: 792 const: zvfbfwma 793 then: 794 allOf: 795 - contains: 796 const: zfbfmin 797 - contains: 798 const: zvfbfmin 799 # Zacas depends on Zaamo 800 - if: 801 contains: 802 const: zacas 803 then: 804 contains: 805 const: zaamo 806 807 - if: 808 contains: 809 const: zve32x 810 then: 811 contains: 812 const: zicsr 813 814 - if: 815 contains: 816 const: zve32f 817 then: 818 allOf: 819 - contains: 820 const: f 821 - contains: 822 const: zve32x 823 824 - if: 825 contains: 826 const: zve64x 827 then: 828 contains: 829 const: zve32x 830 831 - if: 832 contains: 833 const: zve64f 834 then: 835 allOf: 836 - contains: 837 const: f 838 - contains: 839 const: zve32f 840 - contains: 841 const: zve64x 842 843 - if: 844 contains: 845 const: zve64d 846 then: 847 allOf: 848 - contains: 849 const: d 850 - contains: 851 const: zve64f 852 853 - if: 854 contains: 855 anyOf: 856 - const: zvbc 857 - const: zvkn 858 - const: zvknc 859 - const: zvkng 860 - const: zvknhb 861 - const: zvksc 862 then: 863 contains: 864 anyOf: 865 - const: v 866 - const: zve64x 867 868 - if: 869 contains: 870 anyOf: 871 - const: zvbb 872 - const: zvkb 873 - const: zvkg 874 - const: zvkned 875 - const: zvknha 876 - const: zvksed 877 - const: zvksh 878 - const: zvks 879 - const: zvkt 880 then: 881 contains: 882 anyOf: 883 - const: v 884 - const: zve32x 885 886allOf: 887 # Zcf extension does not exist on rv64 888 - if: 889 properties: 890 riscv,isa-extensions: 891 contains: 892 const: zcf 893 riscv,isa-base: 894 contains: 895 const: rv64i 896 then: 897 properties: 898 riscv,isa-extensions: 899 not: 900 contains: 901 const: zcf 902 903additionalProperties: true 904... 905