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/freebsd/sys/contrib/device-tree/src/riscv/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cell
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H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c00
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/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmicrochip-mpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
6 #include "microchip-mpfs-fabric.dtsi"
9 #address-cells = <2>;
10 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
21 i-cache-block-size = <64>;
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H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmicrowatt.dts1 /dts-v1/;
4 #size-cells = <0x02>;
5 #address-cells = <0x02>;
6 model-name = "microwatt";
7 compatible = "microwatt-soc";
13 reserved-memory {
14 #size-cells = <0x02>;
15 #address-cells = <0x02>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
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/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/freebsd/crypto/openssl/util/
H A Dadd-depends.pl2 # Copyright 2018-2021 The OpenSSL Project Authors. All Rights Reserved.
28 my $depext = $target{dep_extension} || ".d";
35 # is, sets $rebuild.
42 ( ( grep { $unified_info{sources}->{$_}->[0] =~ /\.cc?$/ }
44 ( grep { $unified_info{shared_sources}->{$_}->[0] =~ /\.cc?$/ }
77 (my $objfile = shift) =~ s|\.d$|.o|i;
95 if (-f $x) {
103 print STDERR "DEBUG[$producer]: ignoring $objfile <- $line\n"
114 # well with out-of-source-tree builds, so we must resort to tricks
115 # to get things right. Fortunately, the .d files are always placed
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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DTreeTransform.h1 //===------- TreeTransform.h - Semantic Tree Transformation -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
66 /// transformation is performed for non-type template parameters and
69 /// This tree-transformation template uses static polymorphism to allow
86 /// most coarse-grained transformations involve replacing TransformType(),
91 /// For more fine-grained transformations, subclasses can replace any of the
106 /// default locations and entity names used for type-checking
110 /// Private RAII object that helps us forget and then re-remember
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H A DSemaTemplateInstantiate.cpp1 //===------- SemaTemplateInstantiate.cpp - C++ Template Instantiation ------===/
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //===----------------------------------------------------------------------===/
10 //===----------------------------------------------------------------------===/
49 //===----------------------------------------------------------------------===/
51 //===----------------------------------------------------------------------===/
76 return ChangeDecl(CurDecl->getDeclContext()); in UseNextDecl()
95 LambdaCallOperator->getDescribedTemplate()); in getPrimaryTemplateOfGenericLambda()
96 FTD && FTD->getInstantiatedFromMemberTemplate()) { in getPrimaryTemplateOfGenericLambda()
98 FTD->getInstantiatedFromMemberTemplate()->getTemplatedDecl(); in getPrimaryTemplateOfGenericLambda()
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H A DSemaTemplate.cpp1 //===------- SemaTemplate.cpp - Semantic Analysis for C++ Templates -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
55 return SourceRange(Ps[0]->getTemplateLoc(), Ps[N-1]->getRAngleLoc()); in getTemplateParamsRange()
63 for (Scope *TempParamScope = S->getTemplateParamParent(); TempParamScope; in getTemplateDepth()
64 TempParamScope = TempParamScope->getParent()->getTemplateParamParent()) { in getTemplateDepth()
69 auto ParamsAtDepth = [&](unsigned D) { Depth = std::max(Depth, D + 1); }; in getTemplateDepth() argument
75 if (!LSI->TemplateParams.empty()) { in getTemplateDepth()
76 ParamsAtDepth(LSI->AutoTemplateParameterDepth); in getTemplateDepth()
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/freebsd/sys/powerpc/booke/
H A Dtrap_subr.S1 /*-
2 * Copyright (C) 2006-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
29 /*-
72 * SPRG0 - pcpu pointer
73 * SPRG1 - all interrupts except TLB miss, critical, machine check
74 * SPRG2 - critical
75 * SPRG3 - machine check
76 * SPRG4-6 - scratch
80 /* Get the per-CPU data structure */
94 * sprg_sp - SPRG{1-3} reg used to temporarily store the SP
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/freebsd/sys/arm/include/
H A Darmreg.h3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
7 * Copyright (c) 1994-1996 Mark Brinicombe.
69 /* The high-order byte is always the implementor */
72 #define CPU_ID_DEC 0x44000000 /* 'D' */
88 /* On recent ARMs this byte holds the architecture and variant (sub-model) */
145 /* XXX: Cortex-A1
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/freebsd/sys/amd64/amd64/
H A Dpmap.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
47 /*-
49 * Copyright (c) 2014-2020 The FreeBSD Foundation
55 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
92 * this module may throw away valid virtual-to-physical
94 * of virtual-to-physical mappings must be done as
98 * make virtual-to-physical map invalidates expensive,
181 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI)); in pmap_type_guest()
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H A Dtrap.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
138 [T_NMI] = "non-maskable interrupt trap",
148 [T_XMMFLT] = "SIMD floating-point exception",
173 * 0 - only enable flush on return from NMI if required by vmm.ko (default)
174 * >1 - always flush on return from NMI.
176 * Post-boot, the sysctl indicates if flushing is currently enabled.
235 p = td->td_proc; in trap()
242 type = frame->tf_trapno; in trap()
260 if ((frame->tf_rflags & PSL_I) == 0) { in trap()
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/freebsd/sys/i386/i386/
H A Dtrap.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
135 [T_NMI] = { .ei = false, .msg = "non-maskable interrupt trap" },
145 [T_XMMFLT] = { .ei = true, .msg = "SIMD floating-point exception" },
204 panic("td %p stack %#x not in kstack VA %#x %d", in trap_check_kstack()
205 td, stk, td->td_kstack, td->td_kstack_pages); in trap_check_kstack()
231 p = td->td_proc; in trap()
235 type = frame->tf_trapno; in trap()
238 ("trap: interrupts enabled, type %d frame %p", type, frame)); in trap()
266 * executing the probe, DTrace blocks re-scheduling and sets in trap()
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H A Dpmap.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
45 /*-
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
89 * this module may throw away valid virtual-to-physical
91 * of virtual-to-physical mappings must be done as
95 * make virtual-to-physical map invalidates expensive,
192 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
205 static int pgeflag = 0; /* PG_G or-in */
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/freebsd/sys/x86/x86/
H A Dmca.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
100 static int mca_banks; /* Number of per-CPU register banks. */
101 static int mca_maxcount = -1; /* Limit on records stored. (-1 = unlimited) */
116 "Administrative toggle for logging of level one TLB parity (L1TP) errors");
197 static int amd_elvt = -1;
206 * The RASCap register is wholly reserved in families 0x10-0x15 (through model 1F). in amd_thresholding_supported()
259 if (error || req->newptr == NULL) in sysctl_positive_int()
290 record = rec->rec; in sysctl_mca_records()
307 return ("D"); in mca_error_ttype()
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/freebsd/sys/powerpc/powerpc/
H A Dtrap.c1 /*-
81 sizeof(struct callframe) - 3*sizeof(register_t))) /* more args go here */
128 { EXC_FPU, "floating-point unavailable" },
131 { EXC_FIT, "fixed-interval timer" },
135 { EXC_FPA, "floating-point assist" },
142 { EXC_ITMISS, "instruction tlb miss" },
143 { EXC_DLMISS, "data load tlb miss" },
144 { EXC_DSMISS, "data store tlb miss" },
184 for (pe = powerpc_exceptions; pe->vector != EXC_LAST; pe++) { in trapname()
185 if (pe->vector == vector) in trapname()
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/freebsd/sys/dev/agp/
H A Dagp.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
154 gatt->ag_entries = entries; in agp_alloc_gatt()
155 gatt->ag_virtual = kmem_alloc_contig(entries * sizeof(uint32_t), in agp_alloc_gatt()
157 if (!gatt->ag_virtual) { in agp_alloc_gatt()
163 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual); in agp_alloc_gatt()
171 kmem_free(gatt->ag_virtual, gatt->ag_entries * sizeof(uint32_t)); in agp_free_gatt()
189 * Sets the PCI resource which represents the AGP aperture.
199 sc->as_aperture_rid = rid; in agp_set_aperture_resource()
215 if (sc->as_aperture_rid != -1) { in agp_generic_attach()
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/freebsd/sys/powerpc/aim/
H A Dmmu_radix.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 #include <powerpc/pseries/phyp-hvcall.h>
94 #define PPC_BITLSHIFT(bit) (sizeof(long)*NBBY - 1 - (bit))
115 #define NLS_MASK ((1UL<<5)-1)
117 #define RPTE_MASK (RPTE_ENTRIES-1)
120 #define NLB_MASK (((1UL<<52)-1) << 8)
129 #define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */
180 #define TLBIE_RIC_INVALIDATE_TLB 0x0 /* Invalidate just TLB */
182 #define TLBIE_RIC_INVALIDATE_ALL 0x2 /* Invalidate TLB, PWC,
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/freebsd/sys/arm64/arm64/
H A Dpmap.c1 /*-
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
52 /*-
59 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
90 * this module may throw away valid virtual-to-physical
92 * of virtual-to-physical mappings must be done as
96 * make virtual-to-physical map invalidates expensive,
160 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
161 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
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/freebsd/sys/arm/arm/
H A Dpmap-v6.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause
7 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
8 * Copyright (c) 2014-2016 Svatopluk Kraus <skra@FreeBSD.org>
9 * Copyright (c) 2014-2016 Michal Meloun <mmel@FreeBSD.org>
40 /*-
47 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
78 * this module may throw away valid virtual-to-physical
80 * of virtual-to-physical mappings must be done as
84 * make virtual-to-physical map invalidates expensive,
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Features.td1 //=- AArch64Features.td - Describe AArch64 SubtargetFeatures -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
17 string TargetFeatureName, // String used for -target-feature, unless overridden.
28 // The user visible name used by -march/-mcpu modifiers and target attribute
37 // An Extension that can be toggled via a '-march'/'-mcpu' modifier or a target
40 …string TargetFeatureName, // String used for -target-feature and -march, unless overrid…
47 // used for -target-feature. However, there are exceptions. Therefore we
62 //===----------------------------------------------------------------------===//
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